EA-EDU-009 Embedded Artists, EA-EDU-009 Datasheet - Page 17

• Manufacturer Part Number: EA-EDU-009
• Description: MCU, MPU & DSP Development Tools LPC2103 EDUCATION BRD
• Manufacturer: Embedded Artists

Specifications of EA-EDU-009

• Processor To Be Evaluated: LPC2103
• Data Bus Width: 16 bit, 32 bit
• Interface Type: I2C, SPI, UART
• Core: ARM7TDMI-S
• Dimensions: 68 mm x 42 mm
• Maximum Operating Temperature: + 85 C
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
LPC2101_02_03_4
Product data sheet
6.16.1 Features
6.17.1 Crystal oscillator
6.17.2 PLL
6.16 Real-time clock
6.17 System control
The Real-Time Clock (RTC) is designed to provide a set of counters to measure time
when normal or idle operating mode is selected. The RTC has been designed to use little
power, making it suitable for battery powered systems where the CPU is not running
continuously (Idle mode).
The on-chip integrated oscillator operates with external crystal in range of 1 MHz to
25 MHz. The oscillator output frequency is called f
frequency is referred to as CCLK for purposes of rate equations, etc. f
the same value unless the PLL is running and connected. Refer to
and
The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input
frequency is multiplied up into the range of 10 MHz to 70 MHz with a Current Controlled
Oscillator (CCO). The multiplier can be an integer value from 1 to 32 (in practice, the
multiplier value cannot be higher than 6 on this family of microcontrollers due to the upper
frequency limit of the CPU). The CCO operates in the range of 156 MHz to 320 MHz, so
there is an additional divider in the loop to keep the CCO within its frequency range while
the PLL is providing the desired output frequency. The output divider may be set to divide
by 2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2,
it is insured that the PLL output has a 50 % duty cycle. The PLL is turned off and
bypassed following a chip reset and may be enabled by software. The program must
configure and activate the PLL, wait for the PLL to lock, and then connect to the PLL as a
clock source. The PLL settling time is 100 s.
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Incorrect/Incomplete feed sequence causes reset/interrupt if enabled.
Flag to indicate watchdog reset.
Programmable 32-bit timer with internal pre-scaler.
Selectable time period from (T
T
Measures the passage of time to maintain a calendar and clock.
Ultra-low power design to support battery powered systems.
Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and Day
of Year.
Can use either the RTC dedicated 32 kHz oscillator input or clock derived from the
external crystal/oscillator input at XTAL1. The programmable reference clock divider
allows fine adjustment of the RTC.
Dedicated power supply pin can be connected to a battery or the main 3.3 V.
Section 10.1 “XTAL1 input”
PCLK
4.
Rev. 04 — 2 June 2009
for additional information.
PCLK
256
Single-chip 16-bit/32-bit microcontrollers
4) to (T
osc
and the ARM processor clock
PCLK
LPC2101/02/03
2
32
Section 6.17.2 “PLL”
4) in multiples of
osc
© NXP B.V. 2009. All rights reserved.
and CCLK are
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