EA-EDU-009 Embedded Artists, EA-EDU-009 Datasheet - Page 21

MCU, MPU & DSP Development Tools LPC2103 EDUCATION BRD

EA-EDU-009

Manufacturer Part Number
EA-EDU-009
Description
MCU, MPU & DSP Development Tools LPC2103 EDUCATION BRD
Manufacturer
Embedded Artists
Datasheets

Specifications of EA-EDU-009

Processor To Be Evaluated
LPC2103
Data Bus Width
16 bit, 32 bit
Interface Type
I2C, SPI, UART
Core
ARM7TDMI-S
Dimensions
68 mm x 42 mm
Maximum Operating Temperature
+ 85 C
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
NXP Semiconductors
LPC2101_02_03_4
Product data sheet
6.18.1 EmbeddedICE
6.18.2 RealMonitor
Standard ARM EmbeddedICE logic provides on-chip debug support. The debugging of
the target system requires a host computer running the debugger software and an
EmbeddedICE protocol converter. The EmbeddedICE protocol converter converts the
remote debug protocol commands to the JTAG data needed to access the ARM core.
The ARM core has a debug communication channel function built-in. The debug
communication channel allows a program running on the target to communicate with the
host debugger or another separate host without stopping the program flow or even
entering the debug state. The debug communication channel is accessed as a
coprocessor 14 by the program running on the ARM7TDMI-S core. The debug
communication channel allows the JTAG port to be used for sending and receiving data
without affecting the normal program flow. The debug communication channel data and
control registers are mapped in to addresses in the EmbeddedICE logic. The JTAG clock
(TCK) must be slower than
RealMonitor is a configurable software module, developed by ARM Inc., which enables
real time debug. It is a lightweight debug monitor that runs in the background while users
debug their foreground application. It communicates with the host using the DCC, which is
present in the EmbeddedICE logic. The LPC2101/02/03 contain a specific configuration of
RealMonitor software programmed into the on-chip boot ROM memory.
Rev. 04 — 2 June 2009
1
6
of the CPU clock (CCLK) for the JTAG interface to operate.
Single-chip 16-bit/32-bit microcontrollers
LPC2101/02/03
© NXP B.V. 2009. All rights reserved.
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