AD9398KSTZ-150 Analog Devices Inc, AD9398KSTZ-150 Datasheet - Page 12

• Manufacturer Part Number: AD9398KSTZ-150
• Description: IC,TV/VIDEO CIRCUIT,Video Interface Circuit,CMOS,QFP,100PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of AD9398KSTZ-150

• Applications: Video
• Interface: HDMI
• Voltage - Supply: 3.15 V ~ 3.47 V
• Package / Case: 100-LQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9398/PCBZ - BOARD EVALUATION FOR AD9398
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9398
AUDIO PLL SETUP
Data contained in the audio infoframes, among other registers,
define for the AD9398 HDMI receiver not only the type of
audio, but the sampling frequency (f
contains information about the N and CTS values used to
recreate the clock. With this information, it is possible to
regenerate the audio sampling frequency. The audio clock is
regenerated by dividing the 20-bit CTS value into the TMDS
clock, then multiplying by the 20-bit N value. This yields a
multiple of the sampling frequency of either 128 × f
It is possible for this to be specified up to 1024 × f
Table 9. AD9398 Audio Register Settings
Register
0x01
0x02
0x03
0x34
0x58
128 × f
1
CLOCK
N AND CTS VALUES ARE TRANSMITTED USING THE
AUDIO CLOCK REGENERATION PACKET. VIDEO
CLOCK IS TRANSMITTED ON TMDS CLOCK CHANNEL.
VIDEO
N
S
Bits
7:0
7:4
7:6
5:3
2
4
7
6:4
3
2:0
REGISTER
DIVIDE
SOURCE DEVICE
BY
N
N
Figure 7. N and CTS for Audio Clock
Recommended
Setting
0x00
0x40
01
010
1
0
1
011
0
0**
COUNTER
CYCLE
TIME
CLOCK
TMDS
CTS
N
1
1
S
). The audio infoframe also
Function
PLL Divisor (MSBs)
PLL Divisor (LSBs)
VCO Range
Charge Pump Current
PLL Enable
Audio Frequency Mode
Override
PLL Enable
MCLK PLL Divisor
N/CTS Disable
MCLK Sampling Frequency
DIVIDE
CTS
BY
SINK DEVICE
MULTIPLY
S
.
BY
N
S
or 256 × f
128 × f
Rev. 0 | Page 12 of 44
S
S
.
Comments
The analog video PLL is also used for the audio clock circuit when in
HDMI mode. This is done automatically.
In HDMI mode, this bit enables a lower frequency to be used for
audio MCLK generation.
Allows the chip to determine the low frequency mode of the audio
PLL.
This enables the analog PLL to be used for audio MCLK generation.
When the analog PLL is enabled for MCLK generation, another
frequency divider is provided. These bits set the divisor to 4.
The N and CTS values should always be enabled.
000 = 128 × f
001 = 256 × f
010 = 384 × f
011 = 512 × f
In order to provide the most flexibility in configuring the audio
sampling clock, an additional PLL is employed. The PLL
characteristics are determined by the loop filter design, the PLL
charge pump current, and the VCO range setting. The loop
filter design is shown in Figure 8.
To fully support all audio modes for all video resolutions up
to 1080p, it is necessary to adjust certain audio-related
registers from their power-on default values.
describes these registers and gives the recommended
settings.
S
S
S
S
8nF
C
P
Figure 8. PLL Loop Filter Detail
FILT
1.5kΩ
R
Z
C
80nF
Z
PV
D
Table 9