AD9398KSTZ-150 Analog Devices Inc, AD9398KSTZ-150 Datasheet - Page 18

• Manufacturer Part Number: AD9398KSTZ-150
• Description: IC,TV/VIDEO CIRCUIT,Video Interface Circuit,CMOS,QFP,100PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of AD9398KSTZ-150

• Applications: Video
• Interface: HDMI
• Voltage - Supply: 3.15 V ~ 3.47 V
• Package / Case: 100-LQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9398/PCBZ - BOARD EVALUATION FOR AD9398
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9398
Hex Address
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x50
0x56
0x57
0x58
0x59
0x5A
Read/Write
or Read
Only
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read
Bits
[7:0]
[4:0]
[7:0]
[4:0]
[7:0]
[4:0]
[7:0]
[4:0]
[7:0]
[7:0]
[7:0]
[7]
[6]
[3]
[2]
[7]
[6:4]
[3]
[2:0]
[6]
[5]
[4]
[2]
[1]
[0]
[6:0]
Default
Value
10010010
***00000
00000000
***01000
00000000
***01110
10000111
***11000
10111101
00100000
00001111
0*******
*0******
****0***
*****0**
Register Name
CSC_Coeff_B4 LSB
CSC_Coeff_C1 MSB
CSC_Coeff_C1 LSB
CSC_Coeff_C2 MSB
CSC_Coeff_C2 LSB
CSC_Coeff_C3 MSB
CSC_Coeff_C3 LSB
CSC_Coeff_C4 MSB
CSC_Coeff_C4 LSB
Test
Test
A/V Mute Override
AV Mute Value
Disable Video Mute
Disable Audio Mute
MCLK PLL Enable
MCLK PLL_N
N_CTS_Disable
MCLK FS_N
MDA/MCL PU
CLK Term O/R
Manual CLK Term
FIFO Reset UF
FIFO Reset OF
MDA/MCL Three-State
Packet Detected
Rev. 0 | Page 18 of 44
Description
CSC coefficient for equation:
R
G
B
MSB, Register 0x46.
CSC coefficient for equation:
R
G
B
MSB, Register 0x48.
CSC coefficient for equation:
R
G
B
MSB, Register 0x4A.
CSC coefficient for equation:
R
G
B
MSB, Register 0x4C.
CSC coefficient for equation:
R
G
B
Must be written to 0x20 for proper operation.
Must be written to default of 0x0F for proper operation.
A1 overrides the AV mute value with Bit 6.
Disables mute of video during AV mute.
Disables mute of audio during AV mute.
MCLK PLL enable—uses analog PLL.
MCLK PLL N [2:0]—this controls the division of the MCLK
out of the PLL: 0 = /1, 1 = /2, 2 = /3, 3 = /4, and so on.
Prevents the N/CTS packet on the link from writing to
the N and CTS registers.
Controls the multiple of 128 f
0 = 128 f
This disables the MDA/MCL pull-ups.
Clock termination power-down override: 0 = auto,
1 = manual.
Clock termination: 0 = normal, 1 = disconnected.
This bit resets the audio FIFO if underflow is detected.
This bit resets the audio FIFO if overflow is detected.
This bit three-states the MDA/MCL lines.
These 7 bits are updated if any specific packet has been
received since last reset or loss of clock detect. Normal is
0x00.
Bit Data Packet Detected
0
1
2
3
Sets AV mute value if override is enabled.
OUT
OUT
B
OUT
OUT
B
OUT
OUT
B
OUT
OUT
B
OUT
OUT
B
OUT
OUT
OUT
OUT
OUT
= (A1 × R
= (C1 × R
= (A1 × R
= (C1 × R
= (A1 × R
= (C1 × R
= (A1 × R
= (C1 × R
= (A1 × R
= (C1 × R
= (B1 × R
= (B1 × R
= (B1 × R
= (B1 × R
= (B1 × R
AVI infoframe.
Audio infoframe.
SPD infoframe.
MPEG source infoframe.
S
, 1 = 256 f
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
) + (A2 × G
) + (C2 × G
) + (A2 × G
) + (A2 × G
) + (C2 × G
) + (A2 × G
) + (C2 × G
) + (A2 × G
) + (C2 × G
) + (B2 × G
) + (B2 × G
) + (C2 × G
) + (B2 × G
) + (B2 × G
) + (B2 × G
S
, 2 = 384 f
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
) + (C3 × B
) + (C3 × B
) + (C3 × B
) + (A3 × B
) + (B3 × B
) + (A3 × B
) + (B3 × B
) + (C3 × B
) + (A3 × B
) + (B3 × B
) + (C3 × B
) + (A3 × B
) + (B3 × B
) + (A3 × B
) + (B3 × B
S
S
, 7 = 1024 f
used for MCLK out.
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
) + C4
) + C4
) + B4
) + B4
) + B4
) + B4
) + B4
) + A4
) + A4
) + C4
) + A4
) + C4
) + A4
) + C4
) + A4
S
.