AD9398KSTZ-150 Analog Devices Inc, AD9398KSTZ-150 Datasheet - Page 7

• Manufacturer Part Number: AD9398KSTZ-150
• Description: IC,TV/VIDEO CIRCUIT,Video Interface Circuit,CMOS,QFP,100PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of AD9398KSTZ-150

• Applications: Video
• Interface: HDMI
• Voltage - Supply: 3.15 V ~ 3.47 V
• Package / Case: 100-LQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9398/PCBZ - BOARD EVALUATION FOR AD9398
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pin Type
POWER SUPPLY
CONTROL
HDCP
AUDIO DATA OUTPUTS
DATA ENABLE
RTERM
Table 6. Pin Function Descriptions
Mnemonic
INPUTS
OUTPUTS
Rx0+
Rx0−
Rx1+
Rx1−
Rx2+
Rx2−
RxC+
RxC−
FILT
PWRDN
HSOUT
VSOUT
O/E FIELD
DE
Description
Digital Input Channel 0 True.
Digital Input Channel 0 Complement.
Digital Input Channel 1 True.
Digital Input Channel 1 Complement.
Digital Input Channel 2 True.
Digital input Channel 2 Complement.
These six pins receive three pairs of transition minimized differential signaling (TMDS) pixel data (at 10× the pixel
rate) from a digital graphics transmitter.
Digital Data Clock True.
Digital Data Clock Complement.
This clock pair receives a TMDS clock at 1× pixel data rate.
External Filter Connection.
For proper operation, the audio-clock generator PLL requires an external filter. Connect the filter shown in Figure 8
to this pin. For optimal performance, minimize noise and parasitics on this node. For more information see the
PCB Layout Recommendations section .
Power-Down Control/Three-State Control.
The function of this pin is programmable via Register 0x26 [2:1].
Horizontal Sync Output.
A reconstructed and phase-aligned version of the HSYNC input. Both the polarity and duration of this output can
be programmed via serial bus registers. By maintaining alignment with DATACK and DATA, data timing with
respect to horizontal sync can always be determined.
Vertical Sync Output.
The separated VSYNC from a composite signal or a direct pass through of the VSYNC signal. The polarity of this
output can be controlled via the serial bus bit (Register 0x24 [6]).
Odd/Even Field Bit for Interlaced Video. This output identifies whether the current field (in an interlaced signal) is
odd or even. The polarity of this signal is programmable via Register 0x24[4].
Data Enable that defines valid video. Can be received in the signal or generated by the AD9398.
Pin No.
80, 76, 72, 67, 45, 33
100, 90, 10
59, 56, 54
48, 32, 30
83
82
49
50
51
52
28
27
26
25
24
20
21
22
23
88
46
Mnemonic
V
V
PV
DV
GND
SDA
SCL
DDCSCL
DDCSDA
MCL
MDA
S/PDIF
I
I
I
I
MCLKIN
MCLKOUT
SCLK
LRCLK
DE
RTERM
2
2
2
2
D
DD
S0
S1
S2
S3
DD
DD
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Function
Analog Power Supply and DVI Terminators
Output Power Supply
PLL Power Supply
Digital Logic Power Supply
Ground
Serial Port Data I/O
Serial Port Data Clock
HDCP Slave Serial Port Data Clock
HDCP Slave Serial Port Data I/O
HDCP Master Serial Port Data Clock
HDCP Master Serial Port Data I/O
S/PDIF Digital Audio Output
I
I
I
I
External Reference Audio Clock In
Audio Master Clock Output
Audio Serial Clock Output
Data Output Clock for Left and Right Audio Channels
Data Enable
Sets Internal Termination Resistance
2
2
2
2
S Audio (Channel 1, Channel 2)
S Audio (Channel 3, Channel 4)
S Audio (Channel 5, Channel 6)
S Audio (Channel 7, Channel 8)
Value
3.3 V
1.8 V to 3.3 V
1.8 V
1.8 V
0 V
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
V
V
V
V
V
V
V
V
V
3.3 V CMOS
500 Ω
AD9398
DD
DD
DD
DD
DD
DD
DD
DD
DD