ETHER-1GIG-XP-N3 Lattice, ETHER-1GIG-XP-N3 Datasheet - Page 11

• Manufacturer Part Number: ETHER-1GIG-XP-N3
• Description: Ethernet ICs Gigabit Ethernet MAC
• Manufacturer: Lattice

Specifications of ETHER-1GIG-XP-N3

• Product: Ethernet Controllers
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10/100 and 1Gig Ethernet
Lattice Semiconductor
Media Access Controller User’s Guide
Transmit MAC (Tx MAC)
The Tx MAC is responsible for controlling access to the physical medium. The TxMAC reads data from an external
TxFIFO when it detects an active tx_fifoavail. The Tx MAC then formats this data into an Ethernet packet and
passes it to the G/MII module.
The Tx MAC is disabled while reset_n is low and should only be enabled only after the associated registers are
properly initialized. Once enabled, the Tx MAC will continuously monitor the FIFO interface for an indication that
frame(s) are ready to be transmitted. In the Gigabit mode, Tx MAC and the TxFIFO interface operations are syn-
chronous to sys_clk. In the 10/100 mode, the Tx MAC is clocked by tx_clk (supplied from the PHY device). The
TxFIFO interface signals in the 10/100 mode are synchronous to tx_clk.
In 10/100 mode, the Tx MAC can be configured to operate in the half-duplex or full-duplex mode. This is done by
writing to bit[5] of the TX_RX_CTL register. In full-duplex operation, it is possible for the receiver’s buffer to fill up
rapidly. In such cases, the receiver sends flow control (PAUSE) frames to the transmitter, requesting that it stop
transmitting frames. When the receiver is able to free the buffers, the transmitter completes transmitting the current
frame and stops for the duration specified in the PAUSE frame.
Transmitting Frames
By default, the Transmit MAC is configured to generate the FCS pattern for the frame to be transmitted. However,
this can be prevented by setting bit[2] of the Tx_RX_CTL register. This feature is useful if the frames being pre-
sented for transmission already contain the FCS field. When FCS field generation by the MAC is disabled, it is the
user’s responsibility to ensure that short frames are properly padded before the FCS is generated. If the MAC
receives a frame shorter than 64 bytes when FCS generation is disabled, the frame is sent as is and a statistic vec-
tor for the condition is generated.
The DA, SA, L/T, and DATA fields are derived from higher applications through the FIFO interface and then encap-
sulated into an Un-tagged Ethernet frame. This frame is not sent over the network until the network has been idle
for a minimum of Inter Packet Gap (IPG) time. The Frame encapsulation consists of adding the Preamble bits, the
Start of Frame Data (SFD) bits and the CRC check sum to the end of the frame (FCS). If padding is not disabled,
all short frames are padded with hexadecimal AA.
The input signal tx_eof is asserted along with the last set of data transfer to indicate the end of the frame. The Tx
MAC requires a continuous stream of data for the entire frame. There cannot be any bubbles of “no data transfer”
within a frame. The only exception to this rule is the transfer of last set of data which can have only one byte
enabled. If the MAC is able to transmit the frame without any errors, the tx_done signal is asserted. Once the
transmission has ended, data on the tx_stat_vector bus is presented to the host - including all the statistical
information collected in the process of transmitting the frame. Data on this bus is qualified by assertion of the
tx_staten signal.
After the Transmit MAC is done transmitting a frame, it waits for more frames from the FIFO interface. During this
time, it goes to an idle state that can be detected by reading the TX_RX_STS register. Since the MODE register
can be written at any time, the Tx MAC can be disabled while it is actively transmitting a frame. In such cases, the
MAC will completely transmit the current frame and then return to the idle state. The control registers should be
programmed only after the MAC has returned to the IDLE state.
External Transmit FIFO
The interface between the Tx MAC and the FIFO is 16-bit wide. The byte to be transmitted first is presented in posi-
tion 15:8. The byte presented on bits 7:0 will be transmitted next. Within the respective bytes, the bit presented on
positions 15(7) is transmitted first and the bit in position 8(0) is transmitted last. In other words, bit[15]([7]) will be
transmitted on the txd[0] signal of GMII while the bit[8]([0]) will be transmitted on txd[7]. Byte Enable bit[1] corre-
sponds to the byte in position 15:8 and byte enable [0] corresponds to the byte [7:0].
The FIFO signals the MAC if the frame ready for transmission at the head of the FIFO is a Control frame. This is
done so the Tx MAC can continue transmission of a Control frame while it is paused.
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