ETHER-1GIG-XP-N3 Lattice, ETHER-1GIG-XP-N3 Datasheet - Page 23

• Manufacturer Part Number: ETHER-1GIG-XP-N3
• Description: Ethernet ICs Gigabit Ethernet MAC
• Manufacturer: Lattice

Specifications of ETHER-1GIG-XP-N3

• Product: Ethernet Controllers
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
7. Host Interface Read/Write Operation
During a write operation, haddr associated with hdatain, hcs_n and hwrite_n performs a write operation to an
internal register. The end of transaction is indicated by assertion of hready_n. During a read operation, haddr
associated with hcs_n and hread_n forms a write operation. The end of transaction is indicated by the assertion
of hready_n and hdataout_en_n along with the valid read data on hdataout.
Figure 9. Host Interface read/write operation
8. Management Interface Read/Write Operation
During a write operation, mdio_en is asserted and the data is transmitted on mdo. During a read operation,
mdio_en is asserted while the address is being transferred. Once this is done, it is de-asserted for rest of the
transfer enabling the PHY to deliver data on mdi.
Figure 10. Management Interface Read and Write Operations
mdio_en
[addr_width-1:0]
[data_width-1:0]
[data_width-1:0]
hdataout_en_n
mdc
mdo
mdi
hready_n
hdataout
hread_n
hwrite_n
hdatain
hcs_n
haddr
hclk
address and write data
OPERATION
WRITE
WRITE OPERATION
ADDR
DATA
A
A
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Media Access Controller User’s Guide
address of register being read
ADDR
READ OPERATION
DATA B
B
OPERATION
READ
10/100 and 1Gig Ethernet
read data