ETHER-1GIG-XP-N3 Lattice, ETHER-1GIG-XP-N3 Datasheet - Page 12

• Manufacturer Part Number: ETHER-1GIG-XP-N3
• Description: Ethernet ICs Gigabit Ethernet MAC
• Manufacturer: Lattice

Specifications of ETHER-1GIG-XP-N3

• Product: Ethernet Controllers
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10/100 and 1Gig Ethernet
Lattice Semiconductor
Media Access Controller User’s Guide
FIFO Under-flow
If a FIFO underflow occurs, the FIFO logic must assert tx_fifoempty. If at least 64 bytes have been transmitted,
the Tx MAC aborts the transmission by asserting tx_er. In addition, the Tx MAC inserts erroneous CRC bits into
the packet to guarantee the receiver will detect the error in the packet. If less than 64 bytes have been transmitted
when the FIFO underflow occurs, the MAC will pad the remaining bytes before ending the transmission. In either
case, the MAC asserts tx_disframe indicating an error during transmission.
Transmitting PAUSE Frame
Two different methods are used for transmitting a PAUSE frame. In the first method, the application layer forms a
PAUSE frame and submits it for transmission via the FIFO. In the other method, the application layer signals the Tx
MAC directly to transmit a PAUSE frame. This is accomplished by asserting tx_sndpausreg. In this case the Tx
MAC will complete transmission of the current packet and then transmit a PAUSE frame with the PAUSE time value
supplied through the tx_sndpaustim bus.
Retries on Collision
When operating in the half-duplex mode, the Transmit MAC has the capability to perform re-transmission of frames
that have experienced in-window collision up to the specified maximum. This is possible because the MAC always
buffers the first 64 bytes of the frame. This feature can be disabled by setting bit[6] of the TX_RX_CTL register.
When retries are disabled, it is the application software’s responsibility to perform retries of collided packets.
If the MAC has been disabled while it is backing off (soon after a collision), it will only return to the IDLE state after
it has successfully transmitted the frame or has exceeded the retry limit.
In the 10/100 mode, the Tx MAC provides the following information:
• Whether the frame deferred before transmission
• The number of times the frame experiences collision before transmission.
This information is sent as a part of the statistics vector. For a frame transmitted without any errors, the statistics
vector, qualified by the enable signal, is asserted along with the tx_done signal.
When the frame experiences excessive deference, excessive collision or late collision, the statistics bit for the
appropriate condition is set and the tx_disfrm signal is asserted. This indicates an error condition.
Internal Data Buffer and FIFO Interfaces
In the 10/100 mode, the Transmit and Receive sections each contain FIFOs to handle packets less than 64 bytes
and to provide additional data buffering for normal packets. External Transmit and Receive FIFOs are required to
store variable-length normal packets.
On the transmitting side, the internal FIFO stores the first 64 bytes of the frame. This ensures that the Tri-Speed
MAC can re-transmit the frame automatically without any help from the application software during an in-window
collision. This important feature prevents the propagation of collision information into the application software.
The core provides a feature where the user can block all the frames that are shorter than the minimum frame length
of 64 bytes in the Tri-speed MAC itself. This prevents the collision fragments from reaching the user’s application.
The Receive Section contains an internal buffer to support this feature.
In the Gigabit mode, only the Receive Section includes a FIFO and this support the same functions as in the
10/100 mode. External Transmit and Receive FIFOs are required to store variable-length normal packets.
The Tri-Speed MAC provides two independent interfaces for use with external Transmit and Receive FIFOs. This
feature enables the Tri-Speed MAC to support full duplex operation in either 10/100 or Gigabit mode.
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