ETHER-1GIG-XP-N3 Lattice, ETHER-1GIG-XP-N3 Datasheet - Page 13

• Manufacturer Part Number: ETHER-1GIG-XP-N3
• Description: Ethernet ICs Gigabit Ethernet MAC
• Manufacturer: Lattice

Specifications of ETHER-1GIG-XP-N3

• Product: Ethernet Controllers
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
G/MII Interface
The G/MII module uses the clock supplied by the external PHY. The core implements the standard G/MII interface
to connect to the PCS layer.
The module implementing the interface also converts the data to a format usable by the MAC. In the Gigabit mode,
the 8-bit data at the interface is converted to the 16-bit data path of the MAC. In the 10/100 mode, the 4-bit MII data
is packed and input to the 16-bit MAC.
Although not implemented as a separate module, the Reconciliation Sub-layer is implemented as a part of the
G/MII interface. This module is responsible for passing the data from one clock domain (Tri-Speed MAC) to the
other G/MII.
(Optional) Media Independent Interface Management Module (MIIM)
The MIIM accesses management information from the PHY device and writes to or reads from the PHY registers.
A single MIIM can address up to 32 PHY devices. This module runs off its own clock called mdc. The standard
specifies this clock to be at 2.5 MHz, but PHY devices can accept a 10-MHz mdc clock. Therefore, the Tri-Speed
MAC can have a MIIM that is capable of running at up to 10 MHz.
The MIIM read or write operations are specified in the GMII_MNG_CTL register. This register also specifies the
addressed PHY and the register within the PHY that needs to be accessed. The Command Finished bit in the
GMII_MNG_CTL register is reset as soon as a command to read or write is given. It is set only when the MIIM
module completes the operation. While the interface is busy, the GMII_MNG_CTL register cannot be overwritten,
and all write operations to the register are ignored. For a write operation, the data to be written is stored in the
GMII_MNG_DAT register. For a read operation, the data read from the addressed PHY is stored in this register.
The ready bit in the GMII_MNG_CTL is set at the end of the read/write operation.
Internal Registers
The Tri-Speed MAC internal registers are initialized through the generic Host Interface. These rules apply when
accessing the internal registers:
• In 8-bit Host Interfaces, the individual bytes of the registers are accessed through their corresponding addresses,
• In 16-bit or greater Host Interfaces, only even numbered addresses should be used.
• The reserved bits should be programmed to 0. These bits are invalid, and should be discarded when read.
• All registers except the MODE register can be written into only when the core is in the IDLE state. The MODE
Table 4 lists the Tri-Speed MAC registers accessible via the Host Interface. The registers are either Read/Write
(R/W) or Read Only (RO) for status reporting purposes. The values of the registers immediately after the Reset
Condition is removed from the Tri-Speed MAC (POR Value in Hexadecimal format) are also given.
with the lower address pointing to the lower byte.
register is the only register that can be written after the Tri-Speed MAC is no longer in the Reset condition.
13
Media Access Controller User’s Guide
10/100 and 1Gig Ethernet