ETHER-1GIG-XP-N3 Lattice, ETHER-1GIG-XP-N3 Datasheet - Page 4

• Manufacturer Part Number: ETHER-1GIG-XP-N3
• Description: Ethernet ICs Gigabit Ethernet MAC
• Manufacturer: Lattice

Specifications of ETHER-1GIG-XP-N3

• Product: Ethernet Controllers
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Table 1. Tri-Speed Ethernet MAC Input and Output Signals
Signal Descriptions
Clocks and Reset
sys_clk
rx_appclk
gtx_clk
tx_clk
rx_clk
mdc
reset_n
Host Interface
hcs_n
haddr[7:0]
hdatain[((datawidth-1):0]
hwrite_n
hread_n
hready_n
hdataout_en_n
hdataout[(datawidth-1):0]
Transmit MAC Application Interface
tx_fifodata[15:0]
Port Name
Output
Output
Output
Output
Output
Type
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Active
State
Low
Low
Low
Low
Low
Low
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
System Clock . This is used to clock the host interface in all modes.
In the Gigabit mode, the Tx MAC is clocked by this signal. All the
input and the output signals of the Tx MAC are synchronous to this
clock in the Gigabit mode. The frequency is always at 62.5 MHz.
Receive MAC Application I/F Clock . This clock is used in the
Gigabit mode only. All the outputs driven by the Rx MAC are syn-
chronous to this clock. The clock’s frequency is 62.5 MHz.
Gigabit Transmit Clock . This clock is used in the Gigabit mode
only. The transmit signals that are outputs on the GMII interface are
synchronous to this clock. This clock has a frequency of 125 MHz.
Transmit Clock . This clock is used in the 10/100 Mbps mode only.
The Tx MAC, Tx MAC application interface and the MII are synchro-
nous to this signal. This clock has a frequency of 2.5/25 MHz for
10/100 Mbps operation respectively.
Receive Clock . This clock is an input from the PHY device. In the
Gigabit mode, rx_clk frequency is 125 MHz. rx_clk is divided by
two to provide the clock to the Receive MAC section. In the 10/100
mode, the corresponding rx_clk frequency is 2.5/25 MHz respec-
tively, provided directly to the Receive MAC section. The receive
signals at the GMII interface are always synchronous to rx_clk .
Management Data Clock. This clock is used only when the Man-
agement Interface module is implemented.
Reset. This is an active low signal that resets the internal registers
and internal logic. When activated, the I/O signals are driven to
their inactive levels.
Chip Select . This is an active low signal used to select the core for
register Read/Write operations.
Address . This selects one of the internal registers.
Data Bus Input . The CPU writes to the internal registers through
the data bus.
Host Write . This active low signal is used to write data to the
selected register.
Host Read . This active low signal is used to read data from the
selected register.
Ready . This is an active low signal used to indicate the end of
transfer. For write operations, hready_n is asserted after data is
accepted (written). For read operations hready_n is asserted after
data on the hdataout bus is ready to be driven out.
Data Out Enable . This signal is driven low whenever the Tri-Speed
MAC outputs valid data onto the hdataout bus. This signal can be
used to build a bi-directional data bus.
Data Bus Output . The CPU reads the internal registers through
the data bus.
Transmit FIFO Read Data Bus . The data from the FIFO is pre-
sented on this bus. It is valid only when tx_fifobyten is non-zero.
4
Media Access Controller User’s Guide
Description
10/100 and 1Gig Ethernet