ETHER-1GIG-XP-N3 Lattice, ETHER-1GIG-XP-N3 Datasheet - Page 9

• Manufacturer Part Number: ETHER-1GIG-XP-N3
• Description: Ethernet ICs Gigabit Ethernet MAC
• Manufacturer: Lattice

Specifications of ETHER-1GIG-XP-N3

• Product: Ethernet Controllers
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10/100 and 1Gig Ethernet
Lattice Semiconductor
Media Access Controller User’s Guide
Receiving Frames
The frames received by the Rx MAC are analyzed and the Preamble and SFD bytes are stripped off the frame
before it is transferred to an external FIFO. The interface between the MAC and the FIFO is 16-bit wide. The byte
that was received first is presented on the data bus lines [15:8], with bit[15] mapped to rxd[0] of the GMII bus. The
data bus lines [7:0] carry the following byte, with bit [7] mapped to rxd[0].
The default behavior of the MAC is to transfer the unmodified frame after stripping off the Preamble and SFD bytes.
This behavior can be changed by setting bit [1] of the TX_RX_CTL register. When bit [1] is set, the Rx MAC strips
the Preamble, SFD, FCS bytes and the PAD bytes, if any.
Once the frame is ready to be written into the FIFO, the Rx MAC asserts the rx_write signal, then presents the
data on the rx_dbout bus along with the rx_byten signal to indicate valid bytes are present. The rx_write sig-
nal is asserted as long as the frame is being written. After transferring the entire frame into the FIFO, the Rx MAC
asserts rx_eof indicating the end of the frame. If the frame is received with errors, rx_error is asserted along
with rx_eof. If the frame is received with no errors, rx_error remains de-asserted. In either case, a rich set of
statistics vector is presented, containing information about the frame that was received. The statistics vector bus,
rx_stat, is qualified by the assertion of rx_stat_en.
If the RxFIFO becomes full, rx_fifo_full is asserted and the frame data is lost. Therefore, the FIFO full condi-
tion must be avoided at all times. The rx_fifo_error signal will be asserted along with rx_eof for all frames
written into the FIFO while it is full.
The Rx MAC goes to the IDLE state when it is done receiving the frame. This is indicated by bit[10] of the
TX_RX_STS register. If the Rx MAC is disabled while it is in the process of receiving a frame, it goes to the IDLE
state after it completes the current frame reception.
Address Filtering
The Rx MAC offers several address-filtering methods the user can employ to effectively block unwanted frames. It
also provides a PROMISCUOUS mode, in which all supported filtering schemes are abandoned and the Receive
MAC transfers all the frames irrespective of the address they contain.
By default, the Rx MAC is configured to filter and discard Broadcast and Multicast frames. The MAC can be config-
ured to receive Broadcast frames by setting bit [7] of the RX_TX_CTL register. Multicast frames are received only
when bit [4] of the TX_RX_CTL register is set. When set, the Multicast frames are subject to filtering that is depen-
dent on a hash table lookup. The six middle bits of the most significant byte of the CRC, calculated for the destina-
tion address field of the frame, are used to address one of the 64 bits of the hash table. If the retrieved bit is set, a
Multicast addressed frame is received. If not, it is discarded.
All other regular frames are filtered based on the Rx MAC address programmed into the MAC_ADDR_0,
MAC_ADDR_1 and MAC_ADDR_2 registers.
Filtering based on Frame Length
The default minimum Ethernet frame size is 64 bytes. Any frame smaller than 64 bytes could possibly be a collision
fragment. By default, the Rx MAC is configured to ignore bytes shorter than 64 bytes. The user can configure the
MAC to receive shorter frames by setting bit [8] of the TX_RX_CTL register. Whenever a short frame is received,
the appropriate bit is set in the statistics vector, marking it as a Short frame.
The Rx MAC has been designed to receive frames larger than the standard specified maximum as easily as any
other frame. This ensures the MAC can work in environments that can generate jumbo frames. However, for statis-
tics purposes, the user can set the maximum length of the frame in the MAX_PKT_SIZE register. When a received
frame is larger than the number in this register, bit [31] of the Receive Statistics Vector bus is set, marking it as a
Long frame.
Receiving a PAUSE Frame
When the Rx MAC receives a PAUSE frame, the Tx MAC continues with the current transmission, then pauses for
the duration indicated in the PAUSE time. During this time, the Tx MAC can transmit Control frames.
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