ETHER-1GIG-XP-N3 Lattice, ETHER-1GIG-XP-N3 Datasheet - Page 17

• Manufacturer Part Number: ETHER-1GIG-XP-N3
• Description: Ethernet ICs Gigabit Ethernet MAC
• Manufacturer: Lattice

Specifications of ETHER-1GIG-XP-N3

• Product: Ethernet Controllers
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
GMII Management Register Access Control (R/W)
Mnemonic: GMII_MNG_CTL
POR Value = 0000H.
The GMII Management Access register controls the Management Interface Module. This register can be overwrit-
ten only when the interface is not busy. A write operation will be ignored when the interface is busy.
GMII Management Access Data (R/W)
Mnemonic: GMII_MNG_DAT
POR Value = 0000H.
The contents of this register will be transmitted when a write operation is to be performed. When a read operation
is performed, this register will contain the value that was read from a PHY register. This register should be read
only after the cmd_fin bit in the control register is set.
Multicast Tables (R/W), set of eight
Mnemonic: MLT_TAB_[0-7]
POR Value = 0000H.
When the core is programmed to receive multicast frames, a filtering scheme is used to decide whether the frame
should be received or not. The six middle bits of the most significant byte of the CRC value, calculated for the des-
tination address, are used as a key to the 64-bit hash table. The three most significant bits select one of the eight
tables, and the three least significant bits select a bit. The frame is received only if this bit is set.
Multicast_table_[0-7]
Rsvd
Cmd_fin
RW_phyreg
Phy_add
Rsvd
Reg_add
GMII_dat
Name
Name
Name
Range
Range
15:0
12:8
7:5
4:0
15
14
13
Range
15:0
Reserved.
Command Finished. When high, it means the interface has completed the intended oper-
ation. This bit is set to 0 when the interface is busy.
Read/Write PHY Registers
GMII PHY Address. The address of the accessed PHY Bit 12 is the most significant bit,
and it is the first PHY address bit to be transmitted and received.
Reserved.
GMII Register Address. The address of the register accessed. Bit 4 is the most significant
bit and is the first register address bit to be transmitted or received.
GMII Data. Bit 15 is the most significant bit, corresponding to bit 15 of the accessed regis-
ter.
• When ‘1’ -> write operation
• When ‘0’ -> read operation
Multicast Table. Eight tables that make a 64-bit hash.
17
Media Access Controller User’s Guide
Description
Description
Description
10/100 and 1Gig Ethernet