ETHER-1GIG-XP-N3 Lattice, ETHER-1GIG-XP-N3 Datasheet - Page 24

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ETHER-1GIG-XP-N3

Manufacturer Part Number
ETHER-1GIG-XP-N3
Description
Ethernet ICs Gigabit Ethernet MAC
Manufacturer
Lattice
Datasheet

Specifications of ETHER-1GIG-XP-N3

Product
Ethernet Controllers
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lattice Semiconductor
9. GMII Transmit and Receive Operations (Gigabit Mode)
txd and tx_en are driven synchronous to the gtx_clk during transmit operations. When the frame being trans-
mitted has an error, tx_er is asserted.
When receiving data, rxd and rx_en are sampled on the rising edge of rx_clk. An error in the frame is indicated
when rx_er is asserted.
Figure 11. GMII Transmit and Receive Operations
rxd[0:7]
txd[0:7]
gtx_clk
rx_clk
rx_en
rx_er
tx_en
tx_er
VALID FRAME DATA
VALID FRAME DATA
FRAME WITHOUT
FRAME WITHOUT
ERROR
ERROR
24
Media Access Controller User’s Guide
VALID FRAME DATA
VALID FRAME DATA
FRAME WITH
FRAME WITH
ERROR
ERROR
10/100 and 1Gig Ethernet

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