ETHER-1GIG-XP-N3 Lattice, ETHER-1GIG-XP-N3 Datasheet - Page 18

• Manufacturer Part Number: ETHER-1GIG-XP-N3
• Description: Ethernet ICs Gigabit Ethernet MAC
• Manufacturer: Lattice

Specifications of ETHER-1GIG-XP-N3

• Product: Ethernet Controllers
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Pause Opcode (R/W)
Mnemonic: PAUS_OP
POR Value = 0080H
This register contains the PAUSE Opcode, This will be compared against the Opcode in the received PAUSE
frame. This value will also be included in any PAUSE frame transmitted by the Tri-Speed MAC. Bit 15 is transmitted
first and bit 0 is transmitted last.
Timing Diagrams
The operational timing diagrams applicable to the Tri-speed MAC interfaces are shown below:
1. Reception of a 64-Byte Frame Without Error -Rx MAC Application Interface
(Gigabit Mode)
Figure 3. Reception of a 64-byte Frame Without Error
Pause_OpCode
Name
rx_stat_vector[31:0]
rx_appclk
rx_dbout[15:0]
rx_byte_en[1:0]
rx_stat_en
rx_eof
rx_fifo_error
rx_write
rx_error
Range
15:0
PAUSE Opcode.
1,2
3,4
11
5,6
18
Media Access Controller User’s Guide
Description
59,60 61,62 63,64
11
10/100 and 1Gig Ethernet
Valid
0 0