ETHER-1GIG-XP-N3 Lattice, ETHER-1GIG-XP-N3 Datasheet - Page 5

• Manufacturer Part Number: ETHER-1GIG-XP-N3
• Description: Ethernet ICs Gigabit Ethernet MAC
• Manufacturer: Lattice

Specifications of ETHER-1GIG-XP-N3

• Product: Ethernet Controllers
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Table 1. Tri-Speed Ethernet MAC Input and Output Signals (Continued)
tx_fifobyten[1:0]
tx_fifoavail
tx_fifoeof
tx_fifoempty
tx_sndpaustim[15:0]
tx_sndpausreq
tx_fifoctrl
tx_staten
tx_macread
tx_statvec[30:0]
tx_done
Port Name
Output
Output
Output
Output
Type
Input
Input
Input
Input
Input
Input
Input
Active
State
High
High
High
High
High
High
High
N/A
N/A
N/A
N/A
Transmit FIFO Read Data Byte Enable . The upper bit validates
the upper byte of the transmitted data. The lower bit validates the
lower byte of the transmitted data. The Tri-Speed MAC expects
packed data all the time except for the last word where only one
byte could be valid. The Tri-Speed MAC assumes the natural end of
frame when these bits do not have the value of 2’b11.
Transmit FIFO Data Available . When asserted, this indicates that
the TxFIFO has data ready for transmission.
Transmit FIFO End of Frame . This signal is asserted along with
the last word/byte of frame data indicating the end of the frame.
Transmit FIFO Empty . This indicates that the TxFIFO is empty.
When this signal is asserted and the Tri-Speed MAC is reading the
FIFO, the under-run condition is transferred to the network through
the txer signal.
PAUSE Frame Timer . This indicates the PAUSE time value that
should be sent in the PAUSE frame.
PAUSE Frame Request . When asserted, the Tri-Speed MAC
transmits a PAUSE frame. This is also the qualifying signal for the
tx_sndpausetim bus.
FIFO Control Frame . This signal indicates whether the current
frame in the Transmit FIFO is a control frame or a data frame. It is
qualified by the tx_avail signal. The following values apply:
Transmit Statistics Vector Enable . When asserted, the contents
of the statistics vector bus tx_statvec are valid.
Transmit FIFO Read . This is the Tri-Speed MAC Transmit FIFO
read request, asserted by the Tri-Speed MAC for one clock only
when it intends to read the FIFO.
Transmit Statistics Vector . This includes useful information about
the frame that was just transmitted. The corresponding bit locations
of this bus are defined as follows:
Transmit Done . This signal is asserted for one clock cycle after
transmitting a frame if no errors were present in transmission.
• 1 = Control frame
• 0 = Normal frame
• tx_statvec[0] - UNICAST frame
• tx_statvec[1] - Multicast frame
• tx_statvec[2] - BROACAST frame
• tx_statvec[3] - Bad FCS frame
• tx_statvec[4] - JUMBO frame
• tx_statvec[5] - FIFO under-run
• tx_statvec[6] - PAUSE frame
• tx_statvec[7] - VLAN tagged frame
• tx_statvec[21:8] - Number of bytes in the transmitted frame
• tx_statvec[22] - Deferred transmission
• tx_statvec[23] - Excessive deferred transmission
• tx_statvec[24] - Late collision
• tx_statvec[25] - Excessive collision
• tx_statvec[29:26] - Number of early collisions
• tx_statvec[30] - FCS generation is disabled and a short frame
5
was transmitted
Media Access Controller User’s Guide
Description
10/100 and 1Gig Ethernet