IRF540N_R4942 Fairchild Semiconductor, IRF540N_R4942 Datasheet
IRF540N_R4942
Specifications of IRF540N_R4942
IRF540N_R4942
Related parts for IRF540N_R4942
IRF540N_R4942 Summary of contents
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... CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. ©2002 Fairchild Semiconductor Corporation January 2002 Features • ...
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... CAPACITANCE SPECIFICATIONS Input Capacitance Output Capacitance Reverse Transfer Capacitance Source to Drain Diode Specifications PARAMETER Source to Drain Diode Voltage Reverse Recovery Time Reverse Recovered Charge ©2002 Fairchild Semiconductor Corporation o C, Unless Otherwise Specified SYMBOL TEST CONDITIONS = 250 µ (Figure 11) ...
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... SINGLE PULSE 0. FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE 600 100 V = 10V GS TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION ©2002 Fairchild Semiconductor Corporation 150 175 125 FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT RECTANGULAR PULSE DURATION ( PULSE WIDTH (s) FIGURE 4. PEAK CURRENT CAPABILITY ...
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... PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 2.5 2.0 1.5 1.0 0.5 -80 - JUNCTION TEMPERATURE ( J FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE ©2002 Fairchild Semiconductor Corporation (Continued) SINGLE PULSE T = MAX RATED 100µs 1ms 10ms 100 300 NOTE: Refer to Application Notes AN9321 and AN9322. ...
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... FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT Test Circuits and Waveforms VARY t TO OBTAIN P R REQUIRED PEAK FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT ©2002 Fairchild Semiconductor Corporation (Continued) 4000 1000 80 120 160 160 200 o C) FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE 50V ...
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... Test Circuits and Waveforms g(REF) FIGURE 16. GATE CHARGE TEST CIRCUIT FIGURE 18. SWITCHING TIME TEST CIRCUIT ©2002 Fairchild Semiconductor Corporation (Continued DUT g(REF DUT g(TOT g(10 10V g(TH FIGURE 17. GATE CHARGE WAVEFORMS d(ON 90% 10% 50% PULSE WIDTH FIGURE 19. SWITCHING TIME WAVEFORM V = 20V ...
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... S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.5 VOFF= -1.0) .ENDS NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. ©2002 Fairchild Semiconductor Corporation DPLCAP 10 RSLC2 ...
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... Fairchild Semiconductor Corporation DPLCAP 10 RSLC2 - 6 ESG 8 EVTHRES + ...
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... Fairchild Semiconductor Corporation JUNCTION th RTHERM1 CTHERM1 6 RTHERM2 CTHERM2 5 RTHERM3 CTHERM3 4 RTHERM4 CTHERM4 3 RTHERM5 ...
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... TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended exhaustive list of all such trademarks. ACEx™ FAST Bottomless™ FASTr™ FRFET™ CoolFET™ GlobalOptoisolator™ CROSSVOLT™ GTO™ DenseTrench™ ...