MT45W2MW16BGB-701 IT Micron Technology Inc, MT45W2MW16BGB-701 IT Datasheet - Page 13

• Manufacturer Part Number: MT45W2MW16BGB-701 IT
• Manufacturer: Micron Technology Inc

Specifications of MT45W2MW16BGB-701 IT

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Compliant

Page Mode READ Operation
Figure 7:
Burst Mode Operation
PDF: 09005aef82832fa2/Source: 09005aef82832f5f
32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN
Page Mode READ Operation (ADV = LOW)
Page mode is a performance-enhancing extension to the legacy asynchronous READ
operation. In page-mode-capable products, an initial asynchronous READ access is
performed, and then adjacent addresses can be read quickly by simply changing the
low-order address. Addresses A[3:0] are used to determine the members of the 16-
address CellularRAM page. Any change in addresses A[4] or higher will initiate a new
access time. Figure 7 on page 13 shows the timing for a page mode access.
Page mode takes advantage of the fact that adjacent addresses can be read in a shorter
period of time than random addresses. WRITE operations do not include comparable
page mode functionality.
During asynchronous page mode operation, the CLK input must be held static LOW or
HIGH. CE# must be driven HIGH upon completion of a page mode access. WAIT will be
driven while the device is enabled, and its state should be ignored. Page mode is enabled
by setting RCR[7] to HIGH. ADV must be driven LOW during all page mode READ
accesses.
The CE# LOW time is limited by refresh considerations. CE# must not stay LOW longer
than
Burst mode operations enable high-speed synchronous READ and WRITE operations.
Burst operations consist of a multiclock sequence that must be performed in an ordered
fashion. After CE# goes LOW, the address to access is latched on the next rising edge of
CLK that ADV# is LOW. During this first clock rising edge, WE# indicates whether the
operation is going to be a READ (WE# = HIGH, Figure 8 on page 14) or WRITE
(WE# = LOW, Figure 9 on page 15).
The size of a burst can be specified in the BCR either as fixed-length or continuous.
Fixed-length bursts consist of 4, 8, or 16 words. Continuous bursts have the ability to
start at a specified address and burst through the entire memory. The latency count
stored in the BCR defines the number of clock cycles that elapse before the initial data
value is transferred between the processor and CellularRAM device.
LB#/UB#
Address
Data
WE#
OE#
t
CE#
CEM.
32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Address[0]
t AA
13
D[0]
t APA
Address
[1]
< t CEM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D[1]
t APA
Address
[2]
D[2]
t APA
Address
[3]
D[3]
Bus Operating Modes
Don’t Care
©2007 Micron Technology, Inc. All rights reserved.
t
AA