PCA2002U/10AB/1,00 NXP Semiconductors, PCA2002U/10AB/1,00 Datasheet - Page 5

• Manufacturer Part Number: PCA2002U/10AB/1,00
• Manufacturer: NXP Semiconductors

Specifications of PCA2002U/10AB/1,00

• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
PCA2002_6
Product data sheet
7.3 Reset
7.4 Programming possibilities
Table 3.
After measuring the effective oscillator frequency, the number of correction pulses must
be calculated and stored together with the calibration period in the OTP memory (see
Section
The oscillator frequency can be measured at pad RESET, where a square wave signal
with the frequency of
This frequency shows a jitter every minute or every two minutes, depending on the
programmed calibration period, which originates from the time calibration.
Details on how to measure the oscillator frequency and the programmed inhibition time
are given in
At pin RESET an output signal with a frequency of
Connecting pin RESET to VDD stops the motor drive and opens the motor switches.
After releasing pin RESET, the first motor pulse is generated exactly one period later with
the opposite polarity to the last pulse before stopping. The debounce time for the reset
function is between 31 ms and 62 ms.
Connecting pin RESET to V
frequency is 32 Hz, which can be used to test the mechanical function of the watch.
The programming data is organized in an array of 8-bit words (see
the time calibration, B the setting for the monitor pulses, C is not used and D contains the
type recognition (see
Table 4.
Calibration
period
1 minute
2 minutes
Word
A
B
C
D
7.6).
Bit
1
number of 8192 Hz pulses to be removed
pulse width
type
Time calibration
Words and bits
Section
32 kHz watch circuit with programmable output period and pulse width
All information provided in this document is subject to legal disclaimers.
Correction per step (n = 1)
ppm
2.03
1.017
2
7.10.
Table
------------ -
1024
1
Rev. 06 — 6 May 2010
×
7).
SS
f
osc
3
activates the test mode. In this mode the motor output
is provided.
seconds per day ppm
0.176
0.088
4
output period
5
factory test bit
------------ -
1024
1
Correction per step (n = 127)
258
129
×
f
6
osc
=
32Hz
Table
7
duty
cycle
PCA2002
© NXP B.V. 2010. All rights reserved.
seconds per day
22.3
11.15
is provided.
4). A contains
8
calibration
period
pulse
stretching
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