ISP1362BDFA STEricsson, ISP1362BDFA Datasheet

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ISP1362 Single-chip USB On-The-Go controller Rev. 07 — 29 September 2009 1. General description The ISP1362 is a single-chip Universal Serial Bus (USB) On-The-Go (OTG) controller integrated with the advanced ST-Ericsson slave host controller and the ST-Ericsson ISP1181B peripheral controller. ...

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USB host: Supports integrated physical 4096 bytes of multiconfiguration memory Supports all four types of USB transfers: control, bulk, interrupt and isochronous Supports multiframe buffering for isochronous transfer Supports automatic interrupt polling rate mechanism Supports paired buffering for bulk transfer ...

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Applications The ISP1362 can be used to implement a dual-role USB device in any application, USB host or USB peripheral, depending on the cable connection. If the dual-role device is connected to a typical USB peripheral, it behaves like ...

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... Commercial Package description product code ISP1362BDTM LQFP64; 64 leads; body 10 × 10 × 1 inch tape and reel non-dry pack LQFP64; 64 leads; body 10 × 10 × 1.4 mm single tray non-dry pack ISP1362BDFA ISP1362EEUM TFBGA64; 64 balls; body 6 × 6 × 0.8 mm ISP1362_7 Product data sheet Packing 13 inch tape and reel dry pack Rev. 07 — ...

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POWER-ON RESET RESET H_SUSPEND/ 33 H_WAKEUP 13 18, 63 D[15: ...

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... DGND D10 12 D11 D12 D13 16 Fig 2. Pin configuration LQFP64 Fig 3. Pin configuration TFBGA64 ISP1362_7 Product data sheet ISP1362BDTM 40 ISP1362BDFA 004aaa050 ball A1 ISP1362EEUM index area 004aaa151 Transparent top view Rev. 07 — 29 September 2009 ISP1362 Single-chip USB OTG controller ID H_DP2 H_DM2 OTGMODE X2 X1 ...

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Pin description Table 2. Pin description [1] Symbol Pin LQFP64 TFBGA64 DGND DGND 9 F1 ...

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Table 2. Pin description …continued [1] Symbol Pin LQFP64 TFBGA64 D12 15 J1 D13 16 K1 D14 17 K2 D15 18 J3 DGND TEST0 23 ...

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Table 2. Pin description …continued [1] Symbol Pin LQFP64 TFBGA64 DREQ2 DGND 27 K7 DACK1 28 J8 DACK2 29 K8 INT1 30 J9 INT2 31 K9 RESET 32 K10 H_SUSPEND/ 33 J10 H_WAKEUP D_SUSPEND/ ...

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Table 2. Pin description …continued [1] Symbol Pin LQFP64 TFBGA64 H_PSW1 35 H10 H_PSW2 36 G9 DGND 37 G10 CLKOUT F10 H_OC2 41 E10 H_OC1 D10 X2 44 ...

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Table 2. Pin description …continued [1] Symbol Pin LQFP64 TFBGA64 OTG_DM1 49 A9 OTG_DP1 50 B8 AGND CP_CAP1 53 A7 CP_CAP2 BUS DD(REF5V) DGND 57 A5 ...

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Functional description 7.1 On-The-Go (OTG) controller The OTG controller provides all the control, monitoring and switching functions required in OTG operations. 7.2 Advanced ST-Ericsson slave host controller The advanced ST-Ericsson slave host controller is designed for highly optimized USB ...

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GoodLink Indication of a good USB connection is provided through the GoodLink technology (open-drain, maximum current: 4 mA). During enumeration, LED indicators momentarily blink on corresponding to the enumeration traffic of the ISP1362 ports. The LED also blinks on ...

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Memory organization The buffer memory in the host controller uses a multiconfigurable direct addressing architecture. The 4096 bytes host controller buffer memory is shared by the ISTL0, ISTL1, INTL and ATL buffers. ISTL0 and ISTL1 are used for isochronous ...

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Fig 4. Recommended values of the ISP1362 buffer memory allocation The INTL and ATL buffers use ‘blocked memory management’ scheme to enhance the status and control capability of each and every individual Proprietary Transfer Descriptor (PTD) structure. The INTL and ...

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Fig 5. A sample snapshot of the ATL or INTL memory management scheme Figure 5 provides a snapshot of a sample ATL or INTL buffer area of 256 bytes with a block size of 64 bytes. The HCD may put ...

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PTD. Fig 6. A sample snapshot of the ISTL memory management scheme 8.1.2 Memory organization for the peripheral controller The ISP1362 peripheral controller has a total of 2462 bytes of built-in buffer ...

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Fig 7. Peripheral controller buffer memory organization The buffer memory is configured by DcEndpointConfiguration Registers (ECRs). Although the control endpoint has a fixed configuration, all 16 endpoints (control OUT, control IN and 14 programmable endpoints) must be configured before the ...

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Fig 8. PIO interface between a microprocessor and the ISP1362 8.3 DMA mode The ISP1362 also provides DMA mode for external microprocessors to access the internal buffer memory of the ISP1362. The DMA operation enables data to be transferred between ...

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PIO access to internal control registers Table 5 shows the I/O port addressing in the ISP1362. The complete I/O port address decoding must combine with the chip select signal (CS) and address lines (A1 and A0). The direction of ...

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When A0 = LOW, the microprocessor accesses the data port. When A0 = HIGH, the microprocessor accesses the command port. Fig 11. Access to internal control registers A0/ D[15:0] Fig 12. PIO register access ISP1362_7 Product data sheet ...

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A0/ D[15:0] Command phase A0/ D[15:0] Command phase Fig 13. PIO access for a 16-bit or 32-bit register The following is a sample code for PIO access to internal control registers: unsigned long read_reg32(unsigned ...

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Command phase outport(hc_data,low_word); // Data phase outport(hc_data,hi_word); // Data phase } ...

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Set_DirAddrLen(unsigned int data_length,unsigned int addr) { unsigned long RegData = 0; RegData =(long)(addr&0x7FFF); RegData|=(((long)data_length)<<16); write_reg32(HcDirAddrLen,RegData); } After the proper value is written to the HcDirectAddressLength register, data is accessible from the HcDirectAddressData register (called as HcDirAddr_Port in the following ...

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HC cnt++; } while(cnt<(word_size)); Remark: The HcTransferCounter register counts the number of bytes even though the transfer is in number of words. Therefore, the transfer counter must be set to ...

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HcTransferCounter – If DMACounterEnable of the HcDMAConfiguration register is set (that is, the DMA counter is enabled), HcTransferCounter must be set to the number of bytes to be transferred. • HcDMAConfiguration – Read or write DMA (bit 0) – ...

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OtgInterruptEnable register OTG_TMR_IE B_SE0_SRP_IE A_SRP_DET_IE OTG_RESUME_IE OTG_SUSPND_IE RMT_CONN_IE B_SESS_VLD_IE A_SESS_VLD_IE B_SESS_END_IE A_VBUS_VLD_IE ID_REG_IE OtgInterrupt register OTG_TMR_TIMEOUT B_SE0_SRP A_SRP_DET OTG_RESUME OTG_SUSPND RMT_CONN_C B_SESS_VLD_C A_SESS_VLD_C B_SESS_END_C A_VBUS_VLD_C ID_REG_C HcInterruptEnable register MIE RHSC FNO HcInterruptStatus register level 2 RHSC ...

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Interrupt level 2 (OPR group) contains six possible interrupt events (recorded in the HcInterruptStatus register). When any of these events occurs, the corresponding bit will be set to logic 1, and if the corresponding bit in the HcInterruptEnable register is ...

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DcHardwareConfiguration determines the following features: • Level-triggered or edge-triggered (bit 1) • Output polarity (bit 0) For details on the interrupt logic in the peripheral controller, refer to Control application 8.7.3 Combining INT1 and INT2 In some embedded systems, interrupt ...

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Power-On Reset (POR) When V CC will typically be 800 ns. The pulse is started when V To give a better view of the functionality, dips and t4 to t5. If the dip at t4 ...

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On-The-Go (OTG) controller 10.1 Introduction OTG is a supplement to the Hi-Speed USB (USB 2.0) specification that augments existing USB peripherals by adding to these peripherals limited host capability to support other targeted USB peripherals primarily targeted ...

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If the B-device wants to start a session, it must initiate SRP by ‘data line pulsing’ and ‘V pulsing’. When the A-device detects any of these SRP events, it turns on its V BUS (note that only the A-device is ...

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Set A_SRP_DET_EN (bit 10) of the OtgControl register to logic 1. • Steps to enable the SRP detection by data line pulsing: – Set A_SEL_SRP (bit 9) of the OtgControl register to logic 1. – Set A_SRP_DET_EN (bit 10) ...

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HNP request from the B-device. At this point, the B-device becomes a host and asserts bus reset to start using the bus. The B-device must assert the bus reset (that is, SE0) within the time that the ...

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START id | a_bus_req | (a_sess_vld/ & b_conn/) a_wait_vfall drv_vbus/ loc_conn/ loc_sof a_bus_drop a_peripheral drv_vbus loc_conn loc_sof/ b_conn/ & a_set_b_hnp_en id | a_bus_drop | a_aidl_bdis_tmout a_suspend drv_vbus loc_conn/ loc_sof/ Fig 18. Dual-role A-device state diagram ISP1362_7 Product data ...

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START b_host chrg_vbus/ loc_conn/ loc_sof Fig 19. Dual-role B-device state diagram 10.4.3 HNP implementation and OTG state machine The OTG state machine is the software behind all the OTG functionality implemented in the microprocessor system that is connected ...

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Set the polarity and level-triggering or edge-triggering mode of the HcHardwareConfiguration register (bits 1 and 2, default is level-triggered, active LOW). 2. Set the corresponding bits of the OtgInterruptEnable register (bits some of them). 3. ...

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Table 7. Capacitance The connection of the external capacitor (C Figure 20. Remark: If the internal charge pump is not used, C Fig 20. External capacitors connection 11. USB Host Controller (HC) 11.1 USB states of ...

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USBOperational USBOperational write USBSuspend write Fig 21. USB host controller states of the ISP1362 The USB states are reflected in the HostControllerFunctionalState (HCFS) field of the HcControl register. The HCD is allowed to perform only USB state transitions shown in ...

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Read the HcRhPortStatus[1] and HcRhPortStatus[2] registers. The hexadecimal value of one of the registers must change to 0001 0101h, indicating that a device connection has been detected. 10. Write 32-bit hexadecimal value 0000 0102h into either HcRhPortStatus[1] or HcRhPortStatus[2], ...

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PTD structure will have an offset of 40 bytes (sum of the block size (32 bytes) and the PTD header size (8 bytes)). Because of ...

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Table 9. Generic PTD structure: bit allocation [1] Bit 7 6 Byte 0 Byte 1 CompletionCode[3:0] Byte 2 Byte 3 EndpointNumber[3:0] Byte 4 Byte 5 B5[7] B5[6] Byte 6 reserved Byte 7 [1] All reserved bits must be set to ...

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Table 11. Generic PTD structure: bit description Name Status update by HC B5[6] Ping-Pong No B5[7] Paired No DirToken[1:0] No FunctionAddress[6:0] No B7[7:5] PollingRate No B7[4:0] StartingFrame (interrupt only) B7[7:0] StartingFrame No (ISO only) Table 12. CompletionCode[3:0]: bit description Value ...

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Features of the control and bulk transfer (aperiodic transfer) • A paired PTD is a special feature that provides high performance single endpoint bulk transfer and handles set-up enumeration sequence within 1 ms. A paired PTD consists of two ...

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Step 4 The 16 bytes of data is now a complete PTD with an accompanying payload. This array is then copied into the ATL buffer area. Table 13. Offset Data 11.5.1.5 Step 5 After copying data into the ATL ...

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Overcurrent protection circuit The ISP1362 has a built-in overcurrent protection circuitry. You can enable or disable this feature by setting or resetting AnalogOCEnable (bit 10) of the HcHardwareConfiguration register. If this feature is disabled assumed that there ...

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Using external overcurrent detection circuit When V DD(REF5V) supply, the internal overcurrent detection circuit cannot be used. An external overcurrent detection circuit must be used instead. Nevertheless, regardless of the V an external overcurrent detection circuit can be used ...

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OTG port. Fig 25. Using internal charge pump 11.8.4 Overcurrent detection circuit using external 5 V power source in OTG mode In OTG mode using external 5 V ...

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USB peripheral controller The design of the peripheral controller in the ISP1362 is compatible with the ST-Ericsson ISP1181B USB full-speed interface device IC. The functionality of the peripheral controller in the ISP1362 is similar to the ISP1181B in 16-bit ...

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If the endpoint is enabled, the SIE checks the contents of the ESR. If the endpoint is empty, the data from USB is stored in the buffer memory during the data phase else a NAK handshake is sent. 4. ...

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The DMA count is complete. • DMAEN = 0. Remark: If the OneDMA bit in the HcHardwareConfiguration register is set to logic 1, peripheral controller DMA controller handshake signals DREQ2 and DACK2 are routed to DREQ1 and DACK1. When ...

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The following bits of the DcEndpointConfiguration register (ECR) affect the buffer memory allocation: • Endpoint enable bit (FIFOEN) • Size bits of an enabled endpoint (FFOSZ[3:0]) • Isochronous bit of an enabled endpoint (FFOISO) Remark: A register change that affects ...

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Table 17. Physical size (bytes) Logical size (bytes) 16 128 128 12.3.4 Endpoint initialization In response to standard USB request Set Interface, the firmware must program all the 16 ECRs of the peripheral controller in sequence (see enabled or not. ...

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Peripheral controller DMA transfer Direct Memory Access (DMA method to transfer data from one location to another in a computer system, without the intervention of the CPU. Many different implementations of DMA exist. The peripheral controller supports ...

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Table 19. Symbol Description DREQ2 DMA request of peripheral controller O DACK2 DMA acknowledge of peripheral controller EOT end of transfer RD read strobe WR write strobe The DMA subsystem of an IBM-compatible PC is based on the Intel 8237 ...

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The peripheral controller now places the word to be transferred on the data bus lines because its RD signal was asserted by the 8237. 8. The 8237 waits one DMA clock period and then deasserts MEMW and IOR. This ...

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Table 20. EOT condition DcDMACounter register Short packet DMAEN bit of the DcDMAConfiguration register [1] The DMA transfer stops. No interrupt, however, is generated. 12.4.3.2 Isochronous endpoints A DMA transfer to or from an isochronous endpoint can be terminated by ...

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All the input pins of the peripheral controller in the ISP1362 must have a CMOS logic 0 or logic 1 level the interrupt service routine, the firmware must check the current status of the USB bus. When ...

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D — indicates remote wake-up. The ISP1362 will drive a K-state on the USB bus for 10 ms after the D_SUSPEND/D_WAKEUP pin goes LOW or the CS pin goes LOW. 12.5.2 Resume conditions Wake-up from the suspend state is initiated ...

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Table 23. OtgControl register: bit allocation Bit 15 14 Symbol Reset - - Access - - Bit 7 6 Symbol LOC_ LOC_ PULLDN_ PULLDN_ DM DP Reset 1 1 Access R/W R/W Table 24. Bit Symbol ...

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Table 24. Bit Symbol 4 LOC_CONN 3 SEL_CP_ EXT 2 DISCHRG_ VBUS 1 CHRG_VBUS This bit is for the B-device only. If set, it will charge V 0 DRV_VBUS 13.2 OtgStatus register (R: 67h) Code (Hex): 67 — read only ...

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Table 26. Bit 13.3 OtgInterrupt register (R/W: 68h/E8h) Code (Hex): 68 — read Code (Hex): E8 — write Table 27. OtgInterrupt register: bit allocation Bit 15 14 Symbol Reset - - ...

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Table 28. Bit ISP1362_7 Product data sheet OtgInterrupt register: bit description Symbol Description - reserved OTG_TMR_ This bit is set whenever the OTG timer attains time-out. Writing logic 1 ...

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Table 28. Bit 13.4 OtgInterruptEnable register (R/W: 69h/E9h) Code (Hex): 69 — read Code (Hex): E9 — write Table 29. OtgInterruptEnable register: bit allocation Bit 15 14 Symbol Reset - - Access - - Bit 7 6 ...

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Table 30. Bit Symbol 6 OTG_SUSPND_IE 5 RMT_CONN_IE 4 B_SESS_VLD_IE 3 A_SESS_VLD_IE 2 B_SESS_END_IE 1 A_VBUS_VLD_IE 0 ID_REG_IE 13.5 OtgTimer register (R/W: 6Ah/EAh) Code (Hex): 6A — read Code (Hex): EA — write Table 31. OtgTimer register: bit allocation Bit ...

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Table 32. Bit 13.6 OtgAltTimer register (R/W: 6Ch/ECh) Code (Hex): 6C — read Code (Hex): EC — write Table 33. OtgAltTimer register: bit allocation Bit 31 30 Symbol START_ TMR Reset 0 - ...

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Table 34. Bit 14. Host controller registers The host controller contains a set of on-chip control registers. These registers can be read or written by the Host Controller Driver (HCD). The operational registers ...

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Table 35. Host controller registers overview Command (Hex) Register Read Write 12 92 HcRhDescriptorA 13 93 HcRhDescriptorB 14 94 HcRhStatus 15 95 HcRhPortStatus[ HcRhPortStatus[ HcHardwareConfiguration 21 A1 HcDMAConfiguration 22 A2 HcTransferCounter 24 A4 HcμPInterrupt 25 A5 ...

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HC control and status registers 14.1.1 HcRevision register (R: 00h) The bit allocation of the HcRevision register is given in Code (Hex): 00 — read only Table 36. HcRevision register: bit allocation Bit 31 30 Symbol Reset - - ...

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Bit 23 22 Symbol Reset - - Access - - Bit 15 14 Symbol Reset - - Access - - Bit 7 6 Symbol HCFS[1:0] Reset 0 0 Access R/W R/W Table 39. Bit ...

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HcCommandStatus register (R/W: 02h/82h) The HcCommandStatus register is a 4-byte register, and the bit allocation is given in Table 40. This register is used by the host controller to receive commands issued by the HCD, and it also reflects ...

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Table 41. Bit 14.1.4 HcInterruptStatus register (R/W: 03h/83h) This register (bit allocation: hardware interrupts. When an event occurs, the host controller sets the corresponding bit in this register. When a ...

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Table 43. Bit Symbol RHSC 5 FNO 14.1.5 HcInterruptEnable register (R/W: 04h/84h) Each enable bit in the HcInterruptEnable register corresponds to an associated interrupt bit ...

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Bit 23 22 Symbol Reset - - Access - - Bit 15 14 Symbol Reset - - Access - - Bit 7 6 Symbol reserved RHSC Reset - 0 Access - R/W Table 45. Bit ...

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Table 46. HcInterruptDisable register: bit allocation Bit 31 30 Symbol MIE Reset 0 - Access R/W - Bit 23 22 Symbol Reset - - Access - - Bit 15 14 Symbol Reset - - Access - - Bit 7 6 ...

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FrameInterval by writing a new value over the present one at each SOF. This provides the programmability necessary for the host controller to synchronize with an external clocking resource and to adjust any unknown local clock offset. Code ...

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Code (Hex): 8E — write Table 50. HcFmRemaining register: bit allocation Bit 31 30 Symbol FRT Reset 0 - Access R/W - Bit 23 22 Symbol Reset - - Access - - Bit 15 14 Symbol reserved Reset - - ...

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Table 52. HcFmNumber register: bit allocation Bit 31 30 Symbol Reset - - Access - - Bit 23 22 Symbol Reset - - Access - - Bit 15 14 Symbol Reset 0 0 Access R R Bit 7 6 Symbol ...

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Bit 15 14 Symbol Reset - - Access - - Bit 7 6 Symbol Reset 0 0 Access R/W R/W Table 55. Bit 14.3 HC root hub registers All registers included in this partition ...

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Code (Hex): 92 — write Table 56. HcRhDescriptorA register: bit allocation Bit 31 30 Symbol Reset 1 1 Access R/W R/W Bit 23 22 Symbol Reset - - Access - - Bit 15 14 Symbol reserved Reset - - Access ...

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Table 57. Bit 14.3.2 HcRhDescriptorB register (R/W: 13h/93h) The HcRhDescriptorB register is the second of two registers describing the characteristics of the root hub. These fields are written during initialization to correspond to ...

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Table 59. Bit 14.3.3 HcRhStatus register (R/W: 14h/94h) The HcRhStatus register is divided into two parts. The lower word of a double-word represents the hub status field, and ...

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Table 61. Bit Symbol Description 31 CRWE CCIC 16 LPSC 15 DRWE OCI 0 LPS 14.3.4 HcRhPortStatus[1:2] register (R/W [1]: 15h/95h; [2]: 16h/96h) The HcRhPortStatus[1:2] register is used to control ...

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Bit 23 22 Symbol reserved Reset - - Access - - Bit 15 14 Symbol Reset - - Access - - Bit 7 6 Symbol reserved Reset - - Access - - Table 63. Bit ...

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Table 63. Bit ISP1362_7 Product data sheet HcRhPortStatus[1:2] register: bit description Symbol Description CSC ConnectStatusChange: This bit is set whenever a connect or disconnect event occurs. The HCD writes logic ...

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Table 63. Bit ISP1362_7 Product data sheet HcRhPortStatus[1:2] register: bit description Symbol Description POCI On read PortOverCurrentIndicator: This bit is valid only when the root hub is configured in such a way that overcurrent conditions are ...

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HC DMA and interrupt control registers 14.4.1 HcHardwareConfiguration register (R/W: 20h/A0h) The bit allocation of the HcHardwareConfiguration register is given in Code (Hex): 20 — read Code (Hex): A0 — write Table 64. HcHardwareConfiguration register: bit allocation Bit 15 ...

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Table 65. Bit Symbol 10 AnalogOCEnable 9 OneINT 8 DACKMode 7 OneDMA 6 DACKInputPolarity 5 DREQOutputPolarity DataBusWidth[1:0] 2 InterruptOutputPolarity 1 InterruptPinTrigger 0 InterruptPinEnable 14.4.2 HcDMAConfiguration register (R/W: 21h/A1h) Table 66 contains the bit allocation of the HcDMAConfiguration ...

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Bit 7 6 Symbol DMACounter BurstLen[1:0] Enable Reset 0 0 Access R/W R/W Table 67. Bit Symbol DMACounterEnable BurstLen[1:0] 4 DMAEnable Buffer_Type_Select[2:0] See 0 DMAReadWriteSelect Table 68. Bit 3 ...

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Table 69. HcTransferCounter register: bit description Bit Symbol Access Value CounterValue[15:0] R/W 14.4.4 HcμPInterrupt register (R/W: 24h/A4h) All the bits in this register are active at power-on reset. None of the active bits, however, will cause an ...

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Table 71. Bit 14.4.5 HcμPInterruptEnable register (R/W: 25h/A5h) Bits this register are the same as those in the HcμPInterrupt register. The bits in this register are used together with bit ...

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Table 72. HcμPInterruptEnable register: bit allocation Bit 15 14 Symbol Reset - - Access - - Bit 7 6 Symbol INTL_IRQ_ ClkReady Interrupt Enable Reset 0 0 Access R/W R/W Table 73. Bit Symbol OTG_IRQ_InterruptEnable ...

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Code (Hex): 27 — read only Table 74. HcChipID register: bit description Bit Symbol Access CHIPID[15:0] R 14.5.2 HcScratch register (R/W: 28h/A8h) This register is for the HCD to save and restore values when required. The bit ...

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Bit 7 6 Symbol reserved ISTL1_ Active Status Reset - 0 Access - R Table 78. Bit Symbol PairedPTDPingPong 0 — Ping of the paired PTD in ATL is active. 9 ISTL1BufferDone 8 ISTL0BufferDone 7 ...

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Table 79. HcDirectAddressLength register: bit allocation Bit 31 30 Symbol Reset 0 0 Access R/W R/W Bit 23 22 Symbol Reset 0 0 Access R/W R/W Bit 15 14 Symbol reserved Reset 0 0 Access - R/W Bit 7 6 ...

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Code (Hex): B0 — write Table 82. HcISTLBufferSize register: bit description Bit Symbol Access ISTLBufferSize[15:0] R/W 14.7.2 HcISTL0BufferPort register (R/W: 40h/C0h) In addition to the HcDirectAddressData register, the ISP1362 provides this register to act as another data ...

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When the pointer has reached the initialized byte count of the HcTransferCounter register, the host controller sets the AllEOTInterrupt bit in the HcμPInterrupt register to logic 1 and updates the HcBufferStatus register. 14.7.4 HcISTLToggleRate register (R/W: 47h/C7h) The rate of ...

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Code (Hex): 43 — read Code (Hex): C3 — write Table 88. HcINTLBufferPort register: bit description Bit Symbol Access Value DataWord[15:0] R/W The HCD is first required to initialize the HcTransferCounter register with the byte count to ...

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The register is updated once every ms by the host controller and is cleared on read by the HCD. Bits that are set represent its corresponding PTDs are processed by the host controller and the ACK token is received ...

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HcINTLCurrentActivePTD register (R: 1Ah) This register indicates which PTD stored in the INTL buffer is currently active and is updated by the host controller. The HCD can use buffer pointer to decide which PTD locations are ...

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Table 97. HcATLBufferPort register: bit description Bit Symbol Access DataWord[15:0] R/W The HCD is first required to initialize the HcTransferCounter register with the byte count to be transferred and check the HcBufferStatus register. The HCD then sends ...

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Table 100. HcATLPTDDoneMap register: bit description Bit Symbol Access PTDDoneBits R [31:0] 14.9.5 HcATLPTDSkipMap register (R/W: 1Ch/9Ch) This is a 32-bit register, and the bit description is given in represents the first PTD stored in the ATL ...

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Table 103. HcATLCurrentActivePTD register: bit allocation Bit 15 14 Symbol Reset - - Access - - Bit 7 6 Symbol reserved Reset - - Access - - Table 104. HcATLCurrentActivePTD register: bit description Bit ...

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HcATLPTDDoneThresholdTimeOut register (R/W: 52h/D2h) This is a time-out register used to generate an ATL interrupt. The value in this register indicates the maximum allowable time in milliseconds for the host controller to retry a NAK transaction. This register can ...

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If the packet length is odd, the upper byte of the last word endpoint buffer is not transmitted to the host. When reading from an OUT endpoint buffer, the upper byte of the last word must ...

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Table 109. Peripheral controller command and register overview Name Read endpoint n status ( 14) Validate control OUT buffer Validate control IN buffer Validate endpoint n buffer ( 14) buffer memory endpoint 1 to ...

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DcEndpointConfiguration register (R/W: 30h to 3Fh/20h to 2Fh) This command is used to access the DcEndpointConfiguration register (ECR) of the target endpoint. It defines the endpoint type (isochronous or bulk/interrupt), direction (OUT/IN), buffer memory size and buffering scheme. It ...

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Table 112. DcAddress register: bit allocation Bit 7 6 Symbol DEVEN Reset 0 0 Access R/W R/W Table 113. DcAddress register: bit description Bit 15.1.3 DcMode register (R/W: B9h/B8h) This command is used to access the ...

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DcHardwareConfiguration register (R/W: BBh/BAh) This command is used to access the DcHardwareConfiguration register, which consists of 2 bytes. The first (lower) byte contains the device configuration and control values, the second (upper) byte holds clock control bits and the ...

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Table 117. DcHardwareConfiguration register: bit description Bit Symbol 5 DAKPOL WKUPCS INTLVL 0 INTPOL 15.1.5 DcInterruptEnable register (R/W: C3h/C2h) This command is used to individually enable or disable interrupts from all endpoints, as well ...

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Table 119. DcInterruptEnable register: bit description Bit 15.1.6 DcDMAConfiguration (R/W: F1h/F0h) This command defines the DMA configuration of the peripheral controller, and enables or ...

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Table 121. DcDMAConfiguration register: bit description Bit Symbol 15 CNTREN 14 SHORTP EPDIX[3:0] 3 DMAEN BURSTL[1:0] Selects the DMA burst length: 15.1.7 DcDMACounter register (R/W: F3h/F2h) This command ...

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Reset device (F6h) This command resets the peripheral controller in the same way as an external hardware reset by using input RESET. All registers are initialized to their ‘reset’ values. Code (Hex): F6 — reset the device Transaction — ...

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Table 124. Endpoint buffer memory organization Word # 1 (upper byte) … Table 125. Example of endpoint buffer memory access A0 HIGH LOW LOW LOW … Remark: There is no protection against writing ...

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Table 127. DcEndpointStatus register: bit description Bit Symbol 7 EPSTAL 6 EPFULL1 5 EPFULL0 4 DATA_PID 3 OVERWRITE 2 SETUPT 1 CPUBUF 0 - 15.2.3 Stall endpoint or unstall endpoint (40h to 4Fh/80h to 8Fh) These commands are used to ...

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Clear endpoint buffer (70h, 72h to 7Fh) This command unlocks and clears the buffer of the selected OUT endpoint, allowing the reception of new packets. Reception of a complete packet causes the Buffer Full flag of an OUT endpoint ...

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Acknowledge set up (F4h) This command acknowledges to the host that a set-up packet is received. The arrival of a set-up packet disables the Validate Buffer and Clear Buffer commands for the control IN and OUT endpoints. The microprocessor ...

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Table 132. Transaction error codes Error code (Binary) 1000 1001 1010 1011 1100 1101 1110 1111 15.3.2 Unlock Device (B0h) This command unlocks the peripheral controller from write-protection mode after a resume. In the suspend state, all registers and buffer ...

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Code (Hex): B2/B3 — write or read DcScratch register Transaction — write or read 2 bytes (code or data) Table 135. DcScratch Information register: bit allocation Bit 15 14 Symbol reserved Reset - - Access - - Bit 7 6 ...

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Table 139. Example of the DcFrameNumber register access A0 HIGH LOW 15.3.5 DcChipID (R: B5h) This command reads the chip identification code and the hardware version number. The firmware must check this information to determine supported functions and features. This ...

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Table 142. DcInterrupt register: bit allocation Bit 31 30 Symbol Reset - - Access - - Bit 23 22 Symbol EP14 EP13 Reset 0 0 Access R R Bit 15 14 Symbol EP6 EP5 Reset 0 0 Access R R ...

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Limiting values Table 144. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage CC V input voltage I I latch-up current lu V electrostatic discharge voltage esd T storage temperature stg ...

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Static characteristics Table 146. Static characteristics: supply pins 3.6 V; GND = amb Symbol Parameter I operating supply current for CC(HC) the Host Controller I operating supply current for CC(DC) ...

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Table 148. Static characteristics: analog I/O pins (DP 3.6 V; GND = amb Symbol Parameter Input levels V differential input sensitivity DI voltage V differential common mode CM voltage range ...

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Table 149. Static characteristics: charge pump 3.6 V; GND = amb Symbol Parameter I load current LOAD C output capacitance LOAD V V leakage voltage BUS(LEAK) BUS(OTG) I suspend supply current ...

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E efficiency (%) charge pump capacitor. Fig 28. Efficiency as a function of load current 5.2 V BUS (V) 5.0 4.8 4 charge pump capacitor. Fig 29. Output voltage as a ...

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Dynamic characteristics Table 150. Dynamic characteristics 3.6 V; GND = amb Symbol Parameter Reset t pulse width on input RESET W(RESET) Crystal oscillator f crystal frequency xtal R series resistance ...

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Table 152. Dynamic characteristics: charge pump 3.6 V; GND = amb Symbol Parameter t V pulsing time VBUS(PULSE) BUS t V pull-down time VBUS(VALID_dly) BUS V output ripple with constant RIPPLE ...

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15 data D [ 15:0 ] valid Fig 30. Host controller programmed interface timing 19.1.2 Peripheral controller programmed I/O timing Table 154. Dynamic characteristics: peripheral controller programmed interface timing V = ...

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Table 154. Dynamic characteristics: peripheral controller programmed interface timing 3.6 V; GND = amb Symbol Parameter t chip deselect time after WR HIGH WHSH t data set-up time before WR HIGH ...

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A0 t AVWL (2) CS/DACK2 t WLWH WR t DVWH D[15:0] (1) For t , both CS and WR must be deasserted. SHWL (2) Programmable polarity: shown as active LOW. Fig 32. Peripheral controller programmed interface write timing (I/O and ...

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DREQ1 DACK1 D [ 15:0 ] (read 15:0 ] (write Fig 33. Host controller single-cycle DMA timing 19.2.2 Host controller burst mode DMA timing Table 156. Dynamic characteristics: host controller burst mode DMA timing V ...

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DREQ1 t RHSH t RHAL DACK1 Fig 34. Host controller burst mode DMA timing 19.2.3 Peripheral controller single-cycle DMA timing (8237 mode) Table 157. Dynamic characteristics: peripheral controller single-cycle DMA timing (8237 mode 3.0 V ...

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DREQ2 (1) DACK2 DATA (1) Programmable polarity: shown as active LOW. Fig 36. Peripheral controller single-cycle DMA read timing in DACK-only mode 19.2.5 Peripheral controller single-cycle DMA write timing in DACK-only mode Table 159. Dynamic characteristics: peripheral controller single-cycle DMA ...

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Peripheral controller burst mode DMA timing Table 160. Dynamic characteristics: peripheral controller burst mode DMA timing 3.6 V; GND = amb Symbol Parameter t input RD/WR HIGH after DREQ on ...

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Package outline LQFP64: plastic low profile quad flat package; 64 leads; body 1 pin 1 index DIMENSIONS (mm are the original dimensions) A ...

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TFBGA64: plastic thin fine-pitch ball grid array package; 64 balls; body 0.8 mm ball A1 index area ball index area ...

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Abbreviations Table 161. Abbreviations Acronym ACK ASIC AT ATL ATX CMOS CRC DMA DSC ED EHCI EMI EOF EOP EOT ESR GPS HC HCCA HCD HCI HNP INT INTL IS ISO ISR ISTL LS MOSFET MSB NAK OHCI OPR ...

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Table 161. Abbreviations Acronym PMOS POR PORP POST PTD RISC SIE SOF SRP TD USB USBD 22. References [1] On-The-Go Supplement to the USB 2.0 Specification Rev. 1.0a [2] Universal Serial Bus Specification Rev. 2.0 [3] ISP136x Embedded Programming Guide ...

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Revision history Table 162. Revision history Document ID Release date ISP1362_7 20090929 • Modifications: Rebranded to the ST-Ericsson template. • Section 4 “Ordering • Removed soldering information. ISP1362_6 20090121 ISP1362_5 20070508 ISP1362-04 20041224 (9397 750 13957) ISP1362-03 20040106 (9397 ...

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Tables Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .4 Table 2. Pin description . . . . . . . . . ...

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Table 92. HcINTLPTDSkipMap register: bit description .99 Table 93. HcINTLLastPTD register: bit description . . . . .99 Table 94. HcINTLCurrentActivePTD register: bit allocation . . . . . . . . . . . . . . . . ...

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Figures Fig 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Fig 2. Pin configuration LQFP64 . ...

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Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . ...

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Endpoint description . . . . . . . . . . . . . . . . . . . . 51 12.3.1 Endpoints with programmable buffer memory size . . . . . . . . . ...

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Write or read endpoint buffer (R/W: 10h,12h to 1Fh/01h to 0Fh 113 15.2.2 Read endpoint status (R: 50h to 5Fh 114 ...

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... Product data sheet Please Read Carefully: STMicroelectronics NV or Telefonaktiebolaget LM Ericsson. All other names are the property of their respective owners. © ST-Ericsson, 2009 - All rights reserved Contact information at www.stericsson.com under Contacts www.stericsson.com Rev. 07 — 29 September 2009 ISP1362 Single-chip USB OTG controller © ST-ERICSSON 2009. All rights reserved. ...