ISP1362BDFA STEricsson, ISP1362BDFA Datasheet - Page 104

• Manufacturer Part Number: ISP1362BDFA
• Manufacturer: STEricsson

Specifications of ISP1362BDFA

• Lead Free Status / RoHS Status: Compliant

Table 107. HcATLPTDDoneThresholdTimeOut register: bit allocation
15. Peripheral controller registers
ISP1362_7
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
14.9.9 HcATLPTDDoneThresholdTimeOut register (R/W: 52h/D2h)
R/W
15
7
0
-
-
This is a time-out register used to generate an ATL interrupt. The value in this register
indicates the maximum allowable time in milliseconds for the host controller to retry a NAK
transaction. This register can be used in combination with
HcATLPTDDoneThresholdCount.
HcATLPTDDoneThresholdCount register.
Remark: If the time-out indication is not required by the software, or there is no active
PTD in the ATL buffer, write 0000h to this register.
Code (Hex): 52 — read
Code (Hex): D2 — write
Table 108. HcATLPTDDoneThresholdTimeOut register: bit description
The functions and registers of the peripheral controller are accessed using commands,
which consist of a command code followed by optional data bytes (read or write action).
An overview of the available commands and registers is given in
A complete access consists of two phases:
The following applies to a register or buffer memory access in 16-bit bus mode:
Bit
15 to 8
7 to 0
1. Command phase: when address pin A0 = HIGH, the peripheral controller interprets
2. Data phase (optional): when address pin A0 = LOW, the peripheral controller
•
•
the data on the lower byte of the bus (bits D7 to D0) as command code. Commands
without a data phase are immediately executed.
transfers the data on the bus to or from a register or endpoint buffer memory. In case
of multi-byte registers, the least significant byte or word is accessed first.
The upper byte (bits D15 to D8) in the command phase or the undefined byte in the
data phase are ignored.
The access of registers is word-aligned: byte access is not allowed.
R/W
14
6
0
-
-
Symbol
-
PTDDoneTimeOut[7:0] Maximum allowable time in ms for the host controller to retry a
R/W
13
5
0
-
-
Rev. 07 — 29 September 2009
PTDDoneTimeOut[7:0]
R/W
Description
reserved
transaction with NAK returned.
12
4
0
-
-
Table 107
reserved
R/W
shows the bit allocation of the
11
3
0
-
-
Single-chip USB OTG controller
R/W
10
2
0
-
-
Table
© ST-ERICSSON 2009. All rights reserved.
R/W
9
1
0
-
-
109.
ISP1362
104 of 147
R/W
8
0
1
-
-