ISP1362BDFA STEricsson, ISP1362BDFA Datasheet - Page 84

no-image

ISP1362BDFA

Manufacturer Part Number
ISP1362BDFA
Description
Manufacturer
STEricsson
Datasheet

Specifications of ISP1362BDFA

Lead Free Status / RoHS Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ISP1362BDFA
Manufacturer:
STE
Quantity:
5
Part Number:
ISP1362BDFA
Manufacturer:
ST-Ericsson Inc
Quantity:
10 000
ISP1362_7
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
23
15
7
-
-
-
-
-
-
Table 63.
Bit
31 to 21
20
19
18
17
reserved
reserved
22
14
6
-
-
-
-
-
-
Symbol
-
PRSC
OCIC
PSSC
PESC
HcRhPortStatus[1:2] register: bit description
21
13
Description
reserved
PortResetStatusChange: This bit is set at the end of the 10 ms port reset
signal. The HCD writes logic 1 to clear this bit. Writing logic 0 has no effect.
0 — port reset is not complete
1 — port reset is complete
PortOverCurrentIndicatorChange: This bit is valid only if overcurrent
conditions are reported on a per-port basis. This bit is set when the root hub
changes the PortOverCurrentIndicator (POCI) bit. The HCD writes logic 1 to
clear this bit. Writing logic 0 has no effect.
0 — no change in PortOverCurrentIndicator (POCI)
1 — PortOverCurrentIndicator (POCI) has changed
PortSuspendStatusChange: This bit is set when the full resume sequence
is complete. This sequence includes the 20 ms resume pulse, LS EOP and
3 ms re-synchronization delay. The HCD writes logic 1 to clear this bit.
Writing logic 0 has no effect. This bit is also cleared when
PortResetStatusChange is set.
0 — resume is not completed
1 — resume is completed
PortEnableStatusChange: This bit is set when the hardware events cause
the PortEnableStatus (PES) bit to be cleared. Changes from the HCD writes
do not set this bit. The HCD writes logic 1 to clear this bit. Writing logic 0 has
no effect.
0 — no change in PortEnableStatus (PES)
1 — change in PortEnableStatus (PES)
5
-
-
-
-
-
-
Rev. 07 — 29 September 2009
reserved
PRSC
PRS
R/W
R/W
20
12
0
4
0
-
-
OCIC
POCI
R/W
R/W
19
11
0
3
0
-
-
Single-chip USB OTG controller
PSSC
PSS
R/W
R/W
18
10
0
2
0
-
-
PESC
© ST-ERICSSON 2009. All rights reserved.
LSDA
PES
R/W
R/W
R/W
17
0
9
0
1
0
ISP1362
CSC
CCS
R/W
PPS
R/W
R/W
84 of 147
16
0
8
0
0
0

Related parts for ISP1362BDFA