ISP1362BDFA STEricsson, ISP1362BDFA Datasheet - Page 134

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ISP1362BDFA

Manufacturer Part Number
ISP1362BDFA
Description
Manufacturer
STEricsson
Datasheet

Specifications of ISP1362BDFA

Lead Free Status / RoHS Status
Compliant

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Table 159. Dynamic characteristics: peripheral controller single-cycle DMA write timing in DACK-only mode
V
ISP1362_7
Product data sheet
Symbol
t
t
t
t
t
ASRP
ASAP
ASAP
ASDV
APDZ
Fig 36. Peripheral controller single-cycle DMA read timing in DACK-only mode
CC
Fig 37. Peripheral controller single-cycle DMA write timing in DACK-only mode
= 3.0 V to 3.6 V; GND = 0 V; T
+ t
(1) Programmable polarity: shown as active LOW.
(1) Programmable polarity: shown as active LOW.
APRS
DACK2
DACK2
DREQ2
DREQ2
DATA
DATA
19.2.5 Peripheral controller single-cycle DMA write timing in DACK-only mode
Parameter
DREQ2 off after DACK2 on
DACK2 pulse width
DREQ2 on after DACK2 off
data valid after DACK2 on
data hold after DACK2 off
(1)
(1)
amb
=
40
°
C to +85
Rev. 07 — 29 September 2009
Conditions
t
t
t
°
ASRP
ASRP
ASDV
C; unless otherwise specified.
t
ASAP
t
ASAP
t
ASDV
Min
-
25
180
-
-
t
APDZ
t
t
APRS
APRS
t
APDZ
Single-chip USB OTG controller
Typ
-
-
-
-
-
© ST-ERICSSON 2009. All rights reserved.
Max
40
-
-
22
3
ISP1362
004aaa113
004aaa112
134 of 147
Unit
ns
ns
ns
ns
ns

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