ISP1362BDFA STEricsson, ISP1362BDFA Datasheet - Page 13

• Manufacturer Part Number: ISP1362BDFA
• Manufacturer: STEricsson

Specifications of ISP1362BDFA

• Lead Free Status / RoHS Status: Compliant

8. Host and device bus interface
Table 3.
[1]
ISP1362_7
Product data sheet
Priority CS
1
2
3
4
5
Only to enable and disable the bus. Depends only on the DACK signal.
LOW
LOW
HIGH X
HIGH X
HIGH X
Bus access priority table for the ISP1362
7.10 Charge pump
7.9 GoodLink
A1
LOW
HIGH
Indication of a good USB connection is provided through the GoodLink technology
(open-drain, maximum current: 4 mA). During enumeration, LED indicators momentarily
blink on corresponding to the enumeration traffic of the ISP1362 ports. The LED also
blinks on whenever there is valid traffic to the USB ports. In suspend mode, the LED is off.
This feature of GoodLink provides a user-friendly indication on the status of the USB
traffic between the host and the hub, as well as the connected devices. It is a useful
diagnostics tool to isolate faulty equipment, and helps to reduce field support and hotline
costs.
The charge pump generates a 5 V supply from 3.3 V to drive V
an A-device in OTG mode. For details, see
The interface between the external microprocessor and the ISP1362 Host Controller (HC)
and peripheral controller is separately handled by the individual bus interface circuitry.
The host or device automultiplex selects the path for the host access or the device
access. This selection is determined by the A1 address line. For any access to the host
controller or peripheral controller registers, the command phase and the data phase are
needed, which is determined by the A0 address line.
All the functionality of the ISP1362 can be accessed using a group of registers and two
buffer memory areas (one for the host controller and the other for the peripheral
controller). Registers can be accessed using Programmed I/O (PIO) mode. The buffer
memory can be accessed using both PIO and Direct Memory Access (DMA) modes.
When CS is LOW (active), address pin A1 has priority over DREQ and DACK. Therefore,
as long as the CS pin is held LOW, the ISP1362 bus interface does not respond to any
DACK signals. When CS is HIGH (inactive), the bus interface will respond to DREQn and
DACKn. Address pin A1 will be ignored when CS is inactive.
An active DACKn signal when DREQn is inactive will be ignored. If DREQ1, DACK1,
DREQ2 and DACK2 are active, the bus interface will be switched off to avoid potential
data corruption.
Table 3
X
X
DACK1
LOW
X
X
provides the bus access priority for the ISP1362.
DACK2
X
X
X
LOW
X
Rev. 07 — 29 September 2009
DREQ1
X
X
HIGH
LOW
HIGH
DREQ2
X
X
LOW
HIGH
HIGH
Host controller and peripheral controller active
host controller
peripheral controller
host controller
peripheral controller
no driving
Section
10.6.
[1]
Single-chip USB OTG controller
[1]
BUS
when the ISP1362 is
© ST-ERICSSON 2009. All rights reserved.
ISP1362
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