ISP1362BDFA STEricsson, ISP1362BDFA Datasheet - Page 91

• Manufacturer Part Number: ISP1362BDFA
• Manufacturer: STEricsson

Specifications of ISP1362BDFA

• Lead Free Status / RoHS Status: Compliant

ISP1362_7
Product data sheet
14.4.5 HcμPInterruptEnable register (R/W: 25h/A5h)
Table 71.
Bits 9 to 0 in this register are the same as those in the HcμPInterrupt register. The bits in
this register are used together with bit 0 of the HcHardwareConfiguration register to
enable or disable the bits in the HcμPInterrupt register.
At power-on, all the bits in this register are masked with logic 0. This means no interrupt
request output on interrupt pin INT1 can be generated. When a bit is set to logic 1, the
interrupt for that bit is enabled.
The bit allocation of the register is given in
Code (Hex): 25 — read
Code (Hex): A5 — write
Bit
5
4
3
2
1
0
Symbol
HC
Suspended
OPR_Reg
AllEOT
Interrupt
ISTL1_
INT
ISTL0_
INT
SOF_INT
HcμPInterrupt register: bit description
Rev. 07 — 29 September 2009
Description
0 — no event
1 — The host controller has been suspended and no USB activities are
sent from the microprocessor for each ms. The microprocessor can
suspend the host controller by setting bits 6 and 7 of the HcControl
register to logic 1. Once the host controller is suspended, no SOF needs
to be sent to the devices connected to downstream ports.
0 — no event
1 — A host controller operation has caused a hardware interrupt. It is
necessary for the HCD to read the HcInterruptStatus register to determine
the cause of the interrupt.
0 — no event
1 — Data transfer has been completed by using the PIO transfer or the
DMA transfer. This bit is set either when the value of the
HcTransferCounter register has reached zero, or the EOT pin of the host
controller is triggered by an external signal.
0 — no event
1 — The transaction of the last PTD stored in the ISTL1 buffer has been
completed. The microprocessor is required to read data from the ISTL1
buffer. The HCD must first read the HcBufferStatus register to check the
status of the ISTL1 buffer, before reading data to the microprocessor.
0 — no event
1 — The transaction of the last PTD stored in the ISTL0 buffer has been
completed. The microprocessor is required to read data from the ISTL0
buffer. The HCD must first read the HcBufferStatus register to check the
status of the ISTL0 buffer, before reading data to the microprocessor.
0 — no event
1 — The host controller is in the SOF state and it indicates the start of a
new frame. The HCD must first read the HcBufferStatus register to check
the status of the ISTL buffer, before reading data to the microprocessor.
For the microprocessor to perform the DMA transfer of ISO data from or to
the ISTL buffer, the host controller must first initialize the
HcDMAConfiguration register.
Table
…continued
72.
Single-chip USB OTG controller
© ST-ERICSSON 2009. All rights reserved.
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