ISP1362BDFA STEricsson, ISP1362BDFA Datasheet - Page 56

• Manufacturer Part Number: ISP1362BDFA
• Manufacturer: STEricsson

Specifications of ISP1362BDFA

• Lead Free Status / RoHS Status: Compliant

ISP1362_7
Product data sheet
12.4.3.1 Bulk endpoints
12.4.3 End-Of-Transfer conditions
10. The 8237 deasserts the DACK output, indicating that the peripheral controller must
11. The 8237 places bus control signals (MEMR, MEMW, IOR and IOW) and address
12. The CPU acknowledges control of the bus by deasserting HLDA. After activating the
For a typical bulk transfer, the preceding process is repeated 32 times, once for each
word. After each word, the DcAddress register in the DMA controller is incremented by
two and the byte counter is decremented by two. When using the 16-bit DMA, the number
of transfers is 32, and address incrementing and byte counter decrementing is done by
two for each word.
A DMA transfer to or from a bulk endpoint can be terminated by any of the following
conditions (bit names refer to the DcDMAConfiguration register, see
Table
DcDMACounter register — An EOT from the DcDMACounter register is enabled by
setting bit CNTREN of the DcDMAConfiguration register. The peripheral controller has a
16-bit DcDMACounter register, which specifies the number of bytes to be transferred.
When DMA is enabled (DMAEN = 1), the internal DMA counter is loaded with the value
from the DcDMACounter register. When the internal counter completes the transfer as
programmed in the DMA counter, an EOT condition is generated and the DMA operation
stops.
Short packet — Normally, the transfer byte count must be set using a control endpoint
before any DMA transfer takes place. When a short packet has been enabled as an EOT
indicator (SHORTP = 1), the transfer size is determined by the presence of a short packet
in data. This mechanism permits the use of a fully autonomous data transfer protocol.
When reading from an OUT endpoint, reception of a short packet at an OUT token will
stop the DMA operation after transferring the data bytes of this packet.
7. The peripheral controller now places the word to be transferred on the data bus lines
8. The 8237 waits one DMA clock period and then deasserts MEMW and IOR. This
9. The peripheral controller deasserts the DREQ2 signal to indicate to the 8237 that
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because its RD signal was asserted by the 8237.
latches and stores the word at the desired memory location. It also informs the
peripheral controller that the data on the bus lines has been transferred.
DMA is no longer needed. In single cycle mode, this is done after each byte or word;
in burst mode, following the last transferred byte or word of the DMA cycle.
stop placing data on the bus.
lines in 3-state and deasserts the HRQ signal, informing the CPU that it has released
the bus.
bus control lines (MEMR, MEMW, IOR and IOW) and address lines, the CPU
resumes the execution of instructions.
The DMA transfer completes as programmed in the DcDMACounter register
(CNTREN = 1).
A short packet is received on an enabled OUT endpoint (SHORTP = 1).
DMA operation is disabled by clearing the DMAEN bit.
121):
Rev. 07 — 29 September 2009
Single-chip USB OTG controller
© ST-ERICSSON 2009. All rights reserved.
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