ISP1362BDFA STEricsson, ISP1362BDFA Datasheet - Page 98

• Manufacturer Part Number: ISP1362BDFA
• Manufacturer: STEricsson

Specifications of ISP1362BDFA

• Lead Free Status / RoHS Status: Compliant

Table 88.
Table 89.
ISP1362_7
Product data sheet
Bit
15 to 0
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Symbol
DataWord[15:0]
HcINTLBufferPort register: bit description
HcINTLBlkSize register: bit allocation
14.8.3 HcINTLBlkSize register (R/W: 53h/D3h)
14.8.4 HcINTLPTDDoneMap register (R: 17h)
R/W
15
7
0
-
-
Code (Hex): 43 — read
Code (Hex): C3 — write
The HCD is first required to initialize the HcTransferCounter register with the byte count to
be transferred and check the HcBufferStatus register. The HCD then sends the command
(43h to read the INTL buffer, and C3h to write to the INTL buffer) to the host controller
through the I/O port of the microprocessor. After the command is sent, the HCD starts
reading data from the INTL buffer or writing data to the INTL buffer. While the HCD is
accessing the buffer, the buffer pointer of INTL also automatically increases. When the
pointer has reached the initialized byte count of the HcTransferCounter register, the host
controller sets the AllEOTInterrupt bit of the HcμPInterrupt register to logic 1 and updates
the HcBufferStatus register.
The ISP1362 requires the INTL buffer to be partitioned into several equal sized blocks so
that the host controller can skip the current PTD and proceed to process the next PTD
easily. The block size of the INTL buffer is required to be specified in this register and
must be a multiple of 8 bytes. The default value of the block size is 64 bytes, and the
maximum allowable block size is 1024 bytes.
register.
Code (Hex): 53 — read
Code (Hex): D3 — write
Table 90.
This is a 32-bit register, and the bit description is given in
register represents the processing status of a PTD. Bit 0 of the register represents the first
PTD stored in the INTL buffer, bit 1 represents the second PTD stored in the buffer, and so
Bit
15 to 10
9 to 0
Access Value
R/W
R/W
14
6
0
-
-
HcINTLBlkSize register: bit description
Symbol
-
BlockSize[9:0]
0000h
R/W
13
5
0
-
-
Rev. 07 — 29 September 2009
reserved
Description
Data in the INTL buffer to be accessed through this data port.
Description
reserved
The block size of the INTL buffer.
R/W
12
4
0
-
-
BlockSize[7:0]
R/W
11
3
0
-
-
Table 89
shows the bit allocation of the
Single-chip USB OTG controller
R/W
10
2
0
Table
-
-
91. Every bit of the
© ST-ERICSSON 2009. All rights reserved.
R/W
R/W
9
0
1
0
BlockSize[9:8]
ISP1362
R/W
R/W
98 of 147
8
0
0
0