EP2S15F484C3N Altera, EP2S15F484C3N Datasheet - Page 107

• Manufacturer Part Number: EP2S15F484C3N
• Description: IC STRATIX II FPGA 15K 484-FBGA
• Manufacturer: Altera
• Series: Stratix® IIr

Specifications of EP2S15F484C3N

• Number Of Logic Elements/cells: 15600
• Number Of Labs/clbs: 780
• Total Ram Bits: 419328
• Number Of I /o: 342
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Type: Stratix II
• No. Of I/o's: 342
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 550MHz
• Operating Temperature Range: 0°C To +85°C
• Logic Case Style: BGA
• No. Of Pins: 484
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-1874; EP2S15F484C3N

Altera Corporation
May 2007
Notes to
(1)
(2)
(3)
(4)
780-pin
FineLine BGA
1,020-pin
FineLine BGA
1,508-pin
FineLine BGA
1,020-pin
FineLine BGA
1,508-pin
FineLine BGA
Table 2–25. EP2S130 Differential Channels
Table 2–26. EP2S180 Differential Channels
Package
Package
The total number of receiver channels includes the four non-dedicated clock channels that can be optionally used
as data channels.
This is the maximum number of channels the PLLs can directly drive.
This is the maximum number of channels if the device uses cross bank channels from the adjacent center PLL.
The channels accessible by the center fast PLL overlap with the channels accessible by the corner fast PLL.
Therefore, the total number of channels is not the addition of the number of channels accessible by PLLs 1, 2, 3, and
4 with the number of channels accessible by PLLs 7, 8, 9, and 10.
Tables 2–21
Transmitter
Receiver
Transmitter
Receiver
Transmitter
Receiver
Transmitter
Receiver
Transmitter
Receiver
Transmitter/
Transmitter/
Receiver
Receiver
to 2–26:
Channels
Channels
156
156
156
156
64
68
88
92
88
92
Total
Total
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
PLL 1
PLL 1
16
32
17
34
22
44
23
46
37
78
37
78
22
44
23
46
37
78
37
78
Note (1)
Note (1)
Center Fast PLLs
Center Fast PLLs
PLL 2
PLL 2
16
32
17
34
22
44
23
46
41
78
41
78
22
44
23
46
41
78
41
78
PLL 3
PLL 3
16
32
17
34
22
44
23
46
41
78
41
78
22
44
23
46
41
78
41
78
PLL 4
PLL 4
16
32
17
34
22
44
23
46
37
78
37
78
22
44
23
46
37
78
37
78
Stratix II Device Handbook, Volume 1
PLL 7
PLL 7
22
23
37
37
22
23
37
37
-
-
-
-
-
-
-
-
-
-
-
-
Corner Fast PLLs
Corner Fast PLLs
PLL 8
PLL 8
Stratix II Architecture
22
23
41
41
22
23
41
41
-
-
-
-
-
-
-
-
-
-
-
-
PLL 9 PLL 10
PLL 9 PLL 10
22
23
41
41
22
23
41
41
-
-
-
-
-
-
-
-
-
-
-
-
(4)
(4)
22
23
37
37
22
23
37
37
2–99
-
-
-
-
-
-
-
-
-
-