EP2S15F484C3N Altera, EP2S15F484C3N Datasheet - Page 81

• Manufacturer Part Number: EP2S15F484C3N
• Description: IC STRATIX II FPGA 15K 484-FBGA
• Manufacturer: Altera
• Series: Stratix® IIr

Specifications of EP2S15F484C3N

• Number Of Logic Elements/cells: 15600
• Number Of Labs/clbs: 780
• Total Ram Bits: 419328
• Number Of I /o: 342
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Type: Stratix II
• No. Of I/o's: 342
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 550MHz
• Operating Temperature Range: 0°C To +85°C
• Logic Case Style: BGA
• No. Of Pins: 484
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-1874; EP2S15F484C3N

Figure 2–48. Column I/O Block Connection to the Interconnect
Note to
(1)
Altera Corporation
May 2007
The 32 data and control signals consist of eight data out lines: four lines each for DDR applications
io_dataouta[3..0] and io_dataoutb[3..0], four output enables io_oe[3..0], four input clock enables
io_ce_in[3..0], four output clock enables io_ce_out[3..0], four clocks io_clk[3..0], four asynchronous
clear and preset signals io_aclr/apreset[3..0], and four synchronous clear and preset signals
io_sclr/spreset[3..0].
Figure
Local Interconnect
from Logic Array (1)
Interconnects
R4 & R24
Control Signals
2–48:
I/O Block
32 Data &
Interconnect
LAB
LAB Local
Vertical I/O Block
Interconnects
C4 & C16
32
LAB
Note (1)
IO_dataina[3:0]
IO_datainb[3:0]
Stratix II Device Handbook, Volume 1
LAB
Stratix II Architecture
Vertical I/O
Block Contains
up to Four IOEs
io_clk[7..0]
2–73