EP2S15F484C3N Altera, EP2S15F484C3N Datasheet - Page 142

IC STRATIX II FPGA 15K 484-FBGA

EP2S15F484C3N

Manufacturer Part Number
EP2S15F484C3N
Description
IC STRATIX II FPGA 15K 484-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet

Specifications of EP2S15F484C3N

Number Of Logic Elements/cells
15600
Number Of Labs/clbs
780
Total Ram Bits
419328
Number Of I /o
342
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Type
Stratix II
No. Of I/o's
342
I/o Supply Voltage
3.3V
Operating Frequency Max
550MHz
Operating Temperature Range
0°C To +85°C
Logic Case Style
BGA
No. Of Pins
484
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-1874
EP2S15F484C3N

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP2S15F484C3N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP2S15F484C3N
Manufacturer:
ALTERA
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Operating Conditions
5–6
Stratix II Device Handbook, Volume 1
Notes to
(1)
(2)
Notes to
(1)
(2)
V
V
V
V
V
V
V
V
V
V
Table 5–8. 1.8-V I/O Specifications
Table 5–9. 1.5-V I/O Specifications
CCIO
I H
IL
OH
OL
CCIO
I H
IL
OH
OL
Symbol
Symbol
The Stratix II device family’s V
Range of the EIA/JEDEC standard.
This specification is supported across all the programmable drive settings available for this I/O standard as shown
in the Stratix II Architecture chapter in volume 1 of the Stratix II Device Handbook.
The Stratix II device family’s V
Range of the EIA/JEDEC standard.
This specification is supported across all the programmable drive settings available for this I/O standard as shown
in the Stratix II Architecture chapter in volume 1 of the Stratix II Device Handbook.
(1)
(1)
Table
Table
Output supply voltage
High-level input voltage
Low-level input voltage
High-level output voltage
Low-level output voltage
Output supply voltage
High-level input voltage
Low-level input voltage
High-level output voltage
Low-level output voltage
5–8:
5–9:
Parameter
Parameter
Figures 5–1
waveforms, respectively, for all differential I/O standards (LVDS,
LVPECL, and HyperTransport technology).
C C I O
C C I O
voltage level support of 1.8 ± -5% is narrower than defined in the Normal
voltage level support of 1.5 ± -5% is narrower than defined in the Normal
and
I
I
I
I
OH
OL
OH
OL
5–2
= 2 mA
= 2 mA
= –2 mA
= –2 mA
show receiver input and transmitter output
Conditions
Conditions
(2)
(2)
(2)
(2)
0.65 × V
V
0.65 × V
0.75 × V
Minimum
Minimum
CCIO
–0.30
1.425
–0.30
1.71
– 0.45
CCIO
CCIO
CCIO
0.35 × V
V
0.35 × V
0.25 × V
Altera Corporation
Maximum
Maximum
CCIO
1.575
1.89
2.25
0.45
+ 0.30
CCIO
CCIO
CCIO
April 2011
Unit
Unit
V
V
V
V
V
V
V
V
V
V

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