EP2S15F484C3N Altera, EP2S15F484C3N Datasheet - Page 186

• Manufacturer Part Number: EP2S15F484C3N
• Description: IC STRATIX II FPGA 15K 484-FBGA
• Manufacturer: Altera
• Series: Stratix® IIr

Specifications of EP2S15F484C3N

• Number Of Logic Elements/cells: 15600
• Number Of Labs/clbs: 780
• Total Ram Bits: 419328
• Number Of I /o: 342
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Type: Stratix II
• No. Of I/o's: 342
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 550MHz
• Operating Temperature Range: 0°C To +85°C
• Logic Case Style: BGA
• No. Of Pins: 484
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-1874; EP2S15F484C3N

Timing Model
5–50
Stratix II Device Handbook, Volume 1
Note to
(1)
Clock skew adder
EP2S15, EP2S30,
EP2S60
Clock skew adder
EP2S90
Clock skew adder
EP2S130
Clock skew adder
EP2S180
Table 5–68. Clock Network Specifications
This is in addition to intra-clock network skew, which is modeled in the Quartus II software.
Table
(1)
(1)
(1)
(1)
Name
5–68:
Inter-clock network, same side
Inter-clock network, entire chip
Inter-clock network, same side
Inter-clock network, entire chip
Inter-clock network, same side
Inter-clock network, entire chip
Inter-clock network, same side
Inter-clock network, entire chip
Clock Network Skew Adders
The Quartus II software models skew within dedicated clock networks
such as global and regional clocks. Therefore, intra-clock network skew
adder is not specified.
two clock networks driving registers in the IOE.
Description
Table 5–68
specifies the clock skew between any
Min
Typ
Altera Corporation
±100
±110
±125
±150
Max
±50
±55
±63
±75
April 2011
Unit
ps
ps
ps
ps
ps
ps
ps
ps