EP2S15F484C3N Altera, EP2S15F484C3N Datasheet - Page 175

• Manufacturer Part Number: EP2S15F484C3N
• Description: IC STRATIX II FPGA 15K 484-FBGA
• Manufacturer: Altera
• Series: Stratix® IIr

Specifications of EP2S15F484C3N

• Number Of Logic Elements/cells: 15600
• Number Of Labs/clbs: 780
• Total Ram Bits: 419328
• Number Of I /o: 342
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Type: Stratix II
• No. Of I/o's: 342
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 550MHz
• Operating Temperature Range: 0°C To +85°C
• Logic Case Style: BGA
• No. Of Pins: 484
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-1874; EP2S15F484C3N

Altera Corporation
April 2011
Notes to
(1)
(2)
(3)
(4)
(5)
(6)
t
t
t
t
t
t
t
t
t
t
(6)
t
t
t
M 4 K D ATA A S U
M 4 K D ATA A H
M 4 K A D D R A S U
M 4 K A D D R A H
M 4 K D ATA B S U
M 4 K D ATA B H
M 4 K R A D D R B S U
M 4 K R A D D R B H
M 4 K D ATA C O 1
M 4 K D ATA C O 2
M 4 K C L K H
M 4 K C L K L
M 4 K C L R
Table 5–41. M4K Block Internal Timing Microparameters (Part 2 of 2)
Symbol
F
These numbers apply to -3 speed grade EP2S15, EP2S30, EP2S60, and EP2S90 devices.
These numbers apply to -3 speed grade EP2S130 and EP2S180 devices.
For the -3 and -5 speed grades, the minimum timing is for the commercial temperature grade. Only -4 speed grade
devices offer the industrial temperature grade.
For the -4 speed grade, the first number is the minimum timing parameter for industrial devices. The second
number is the minimum timing parameter for commercial devices.
Numbers apply to unpacked memory modes, true dual-port memory modes, and simple dual-port memory modes
that use locally routed or non-identical sources for the A and B port registers.
MAX
Table
of M4K Block obtained using the Quartus II software does not necessarily equal to 1/TM4KRC.
5–41:
A port data setup time
before clock
A port data hold time
after clock
A port address setup
time before clock
A port address hold time
after clock
B port data setup time
before clock
B port data hold time
after clock
B port address setup
time before clock
B port address hold time
after clock
Clock-to-output delay
when using output
registers
Clock-to-output delay
without output registers
Minimum clock high time 1,250
Minimum clock low time
Minimum clear pulse
width
Parameter
1,616 2,453 1,616 2,574 1,540
1,250
Min
203
203
203
203
334
144
(4)
22
22
22
22
Grade
-3 Speed
Max
(2)
524
1,312
1,312
Min
213
213
213
213
334
151
(4)
23
23
23
23
Grade
-3 Speed
Max
(3)
549
Stratix II Device Handbook, Volume 1
1,616
1,437
1,437
1,437
1,437
Min
233
233
233
233
233
233
233
233
319
334
165
165
(5)
25
25
25
25
25
25
25
25
Note (1)
-4 Speed
DC & Switching Characteristics
Grade
2,820 1,616 3,286
Max
601
1,675
1,675
Min
272
272
272
272
334
192
(4)
29
29
29
29
-5 Speed
Grade
Max
701
5–39
Unit
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps