MC68HC000EI16 Freescale Semiconductor, MC68HC000EI16 Datasheet - Page 34

• Manufacturer Part Number: MC68HC000EI16
• Description: IC MPU 32BIT 16MHZ 68-PLCC
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC000EI16

• Processor Type: M680x0 32-Bit
• Speed: 16MHz
• Voltage: 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 16/32Bit
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 68
• Package Type: PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Bus Request (
Bus Grant (
Bus Grant Acknowledge (
3.5 INTERRUPT CONTROL (
These input signals indicate the encoded priority level of the device requesting an
interrupt. Level seven, which cannot be masked, has the highest priority; level zero
indicates that no interrupts are requested. IPL0 is the least significant bit of the encoded
level, and IPL2 is the most significant bit. For each interrupt request, these signals must
remain asserted until the processor signals interrupt acknowledge (FC2–FC0 and A19–
A16 high) for that request to ensure that the interrupt is recognized.
3-6
This input can be wire-ORed with bus request signals from all other devices that could
be bus masters. This signal indicates to the processor that some other device needs to
become the bus master. Bus requests can be issued at any time during a cycle or
between cycles.
This output signal indicates to all other potential bus master devices that the processor
will relinquish bus control at the end of the current bus cycle.
This input indicates that some other device has become the bus master. This signal
should not be asserted until the following conditions are met:
The 48-pin version of the MC68008 has no pin available for the bus grant acknowledge
signal and uses a two-wire bus arbitration scheme instead. If another device in a system
supplies a bus grant acknowledge signal, the bus request input signal to the processor
should be asserted when either the bus request or the bus grant acknowledge from that
device is asserted.
1. A bus grant has been received.
2. Address strobe is inactive, which indicates that the microprocessor is not using the
3. Data transfer acknowledge is inactive, which indicates that neither memory nor
4. Bus grant acknowledge is inactive, which indicates that no other device is still
bus.
peripherals are using the bus.
claiming bus mastership.
BG
The 48-pin version of the MC68008 has only two interrupt
control signals: IPL0/IPL2 and IPL1. IPL0/IPL2 is internally
connected to both IPL0 and IPL2, which provides four interrupt
priority levels: levels 0, 2, 5, and 7. In all other respects, the
interrupt priority levels in this version of the MC68008 are
identical to those levels in the other microprocessors described
in this manual.
).
BR
M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL
).
Freescale Semiconductor, Inc.
For More Information On This Product,
BGACK
Go to: www.freescale.com
IPL0
).
,
IPL1
NOTE
,
IPL2
)
MOTOROLA