MC68030CRC25C Freescale Semiconductor, MC68030CRC25C Datasheet - Page 140

• Manufacturer Part Number: MC68030CRC25C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030CRC25C

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

6.1 O N - C H I P C A C H E O R G A N I Z A T I O N
MOTOROLA
~emulators.
the enable bits in CACR. CDIS is primarily intended for use by in-circuit
Another input signal, cache inhibit in (CIIN), inhibits caching of data reads
that should not be cached are data for I/O devices and data from memory
the required operand.
An output signal, cache inhibit out (CLOUT), reflects the state of the cache
that corresponds to a specified logical address or the transparent translation
Whenever a read access occurs and the required instruction word or data
translation must be available and valid, protections are checked, and the
The tag field for each line contains a valid bit for each entry in the line; each
entry is independently replaceable. When appropriate, the bus controller
control register (CACR) is accessible by supervisor programs to control the
operation of both caches.
System hardware can assert the cache disable (CDIS) signal to disable both
caches. The assertion of CDIS disables the caches, regardless of the state of
or instruction prefetches on a bus-cycle by bus-cycle basis. Examples of data
devices that cannot supply a full port width of data, regardless of the size of
Subsequent paragraphs describe how CIIN is used during the filling of the
caches.
CLOUT is asserted and the instruction and data caches are ignored for the
access. This signal can also be used by external hardware to inhibit caching
operand is resident in the appropriate on-chip cache (no external bus cycle
state of the corresponding CI bits in the MMU are also ignored. The MMU
CLOUT signal is asserted appropriately.
Both on-chip caches are 256-byte direct-mapped caches, each organized as
16 lines. Each line consists of four entries, and each entry contains four bytes.
requests a burst mode operation to replace an entire cache line. The cache
inhibit (CI) bit from the MMU of either the address translation cache entry
register that corresponds to that address. Whenever the appropriate CI bit
is set for either a read or a write access and an external bus cycle is required,
in external caches.
is required), the MMU is completely ignored, unless an invalid translation
resides in the MMU at that time (see next two paragraphs). Therefore, the
is used to validate all accesses that require external bus cycles; an address
MC68030 USER'S MANUAL
A N D O P E R A T I O N
6-3
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