MC68030CRC25C Freescale Semiconductor, MC68030CRC25C Datasheet - Page 163

• Manufacturer Part Number: MC68030CRC25C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030CRC25C

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

7
7-2
for the data.
The bus can operate in an asynchronous mode identical to the MC68020 bus
for any port width. The bus and control input signals used far asynchronous
typical asynchronous input.
the input during a sample window around the falling edge of the clock signal.
This window is illustrated in Figure 7-2. To ensure that an input signal is
time period, the level recognized by the processor is not predictable; how-
address bus that specifies the address for the transfer and a data bus that
transfers the data. Control signals indicate the beginning of the cycle, the
address space and the size of the transfer, and the type of cycle. The selected
device then controls the length of the cycle with the signal(s) used to ter-
data bus, indicate the validity of the address and provide timing information
operation are internally synchronized to the MC68030 clock, introducing a
delay. This delay is the time period required for the MC68030 to sample an
asynchronous input signal, synchronize the input to the internal clocks of the
processor, and determine whether it is high or low. Figure 7-1 shows the
relationship between the clock signal and the associated internal signal of a
recognized on a specific falling edge of the clock, that input must be stable
during the sample window. If an input makes a transition during the window
ever, the processor always resolves the latched level to either a logic high
or low before using it. in addition to meeting input setup and hold times for
deterministic operation, all input signals must obey the protocols described
in this section.
minate the cycle. Strobe signals, one for the address bus and another for the
Furthermore, for all asynchronous inputs, the processor latches the level of
Figure 7-1. Relationship between External and Internal Signals
EXT
CLK
INT
MC68030 USER'S MANUAL
-~
SYNC DELAY
MOTOROLA