MC68030CRC25C Freescale Semiconductor, MC68030CRC25C Datasheet - Page 288

• Manufacturer Part Number: MC68030CRC25C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030CRC25C

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

8.1.10 MMU Configuration Exception
MOTOROLA
M o s t M68000 Family peripherals use programmable interrupt vector num-
the active supervisor stack. The saved value of the program counter is the
the stack so that the MC68030 can continue executing the coprocessor in-
the status register saved on the throwaway frame is exactly the same as that
the S bit set and the M bit cleared.
The processor loads the address in the exception vector into the program
fetches for the interrupt handler routine.
Once the vector number is obtained, the processor saves the exception vector
offset, program counter value, and the internal copy of the status register on
cution of a coprocessor instruction, further internal :information is saved on
struction when the interrupt handler completes execution.
creates a throwaway exception stack frame on top of the interrupt stack as
part of interrupt exception processing. This second frame contains the same
master stack, but has a format number of 1 instead of 0 or 9. The copy of
on the interrupt stack. (It may or may not be set in the copy saved on the
counter, and normal instruction execution resumes after the required pre-
acknowledge an interrupt request, the peripheral usually returns the vector
When the MC68030 executes a PMOVE instruction that attempts to move
struction causes an MMU configuration exception. The exception is a post-
for a description of the valid configurations for the MMU registers.
logical address of the instruction that would have been executed had the
interrupt not occurred. If the interrupt was acknowledged during the exe-
If the M bit of the status register is set, the processor clears the M bit and
program counter value and vector offset as the frame created on top of the
placed on the master stack except that the S bit is set in the version placed
master stack.) The resulting status register (after exception processing) has
bers as part of the interrupt request/acknowledge mechanism of the system.
If this vector number is not initialized after reset and the peripheral must
number for the uninitialized interrupt vector, 15.
invalid data into the TC, CRP, or SRP register of the MMU, the PMOVE in-
instruction exception; it is processed after the instruction completes. The
processor generates exception vector number 56 when an MMU configu-
ration exception occurs. Refer to SECTION 9 MEMORY MANAGEMENT UNIT
MC68030 USER'S MANUAL
8-21
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