MC68030CRC25C Freescale Semiconductor, MC68030CRC25C Datasheet - Page 592

• Manufacturer Part Number: MC68030CRC25C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030CRC25C

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Read/Write Signal, 5-5, 7-4, 7-36ff
Real Time Instruction Trace, 12-39-12-43
Recovery,
REFILl- Signal, 5-10, 6-5
Register Select CIR, 10-32
Registers,
Representation, Internal Operand, 7-8
Request, Bus, 7-98
Requirements, Data Bus, Read Cycle, 7-10
Queue, 2-39
R/W Signal, 5-5, 7-4, 7-36ff
RAM, Static, 12-18-12-24
Ratings, Maximum, 13-1
Read Cycle,
Read-Modify-Write
Register,
Reset,
Protocol
MOTOROLA
Address, 1-6, 2-4
Transparent Translation, 1-9, 2-5, 9-16, 9-55
Asynchronous, 32-Bit Port, Timing, 7-33
Accesses, 6-10
Signal, 5-5, 7-4, 7-36ff, 12-3
RTE, 8-25
Cache Address, 1-9, 2-5, 6-23
Cache Control, 1-9, 2-5, 6-1, 6-3, 6-20, 6-21
Condition Code, 2-4, 3-14
Coprocessor interface, 10-8, 10-29
Status, 1-8, 2-4, 6-5
Translation Control, 1-9, 2-5, 9-8, 9-54
Vector Base, 1-8, 2-5
Data Organization, 2-2
Data, 1-6, 2-2
Function Code, 1-8, 2-5
Cache, 6-20
Violations,
Data Bus Requirements, 7-10
Synchronous, 7-48
Cycle,
Bus Fault, 8-27
MMU Status, 1-9, 2-5, 9-60-9-63
Processor General Instruction, 10-7
Asynchronous, Byte, 32-Bit Port, Timing, 7-45
CIIN Asserted, CRACK Negated, Timing, 7-50
Asynchronous, 7-45
Asynchronous, Flowchart, 7-44
Synchronous, 7-52
Synchronous, CIIN Asserted, Flowchart, 7-56
Synchronous, Flowchart, 7-55
Coprocessor Detected, 10-62
Main Processor Detected, 10-65
- - Q - -
m R - -
MC68030 USER'S MANUAL
RESET Signal, 5-9, 7-97ff, 9-15, 9-61
Resource Scheduling, 11-1
Response CIR, 10-29
Restore CtR, 10-31
Restore Operatio n Timing Table, 11-51
Reset (Continued)
Retry Operation, 7-89
Return from Exception, 8-24
RMC Signal, 5-5, 7-4, 7-36
Root Pointer Descriptor, 9-23
Rotate Instructions, 3-7
Routine,
RTE
Save CIR, 10-30
Save Operation Timing Table, 11-51
ScanPC, 10-15, 10-18, 10-34
Scheduling, Resource, 11-1
Script, Table Search Timing, 11-51
Search, Table, 9-28, 9-30
Sequence, Exception Processing, 8-1
Set, instruction, 1-10, 1-13
Set on Coprocessor Condition Instruction, 10-15
SFC, 1-8, 2-5
Shared Supervisor/User Address Space Logical
Sharing, Table, 9-37, 9-39
Shift Instructions, 3-7
Shift/Rotate Instruction Timing Table, 11-45
Short Format
Side Effects, MMU Register, 9-61
Signal,
Coprocessor, 10-72
Exception, 8-5, 8-6
Operation, 7-103
Signal, 5-9, 7-97ff, 9-15, 9-61
Late,
AbortTask, 9-86
8us Error, 9-84
GetFrame, 9-85
SwapPageln, 9-86
Vallocate, 9-79
Bus Fault Recovery, 8-26
Instruction, 8-24
Address Map, 9-49
Table Descriptor, 9-24
Address Strobe, 5-5, 7-3, 7-4, 7-26ff
AS, 5-5, 7-3, 7-4, 7-26ff
Autovector, 5-8, 7-6, 7-29, 7-71ff
Early Termination Page Descriptor, 9-24
indirect Descriptor, 9~26
Invalid Descriptor, 9-25
Page Descriptor, 9-25
Asynchronous, Timing, 7-90
Burst, Timing, 7-92
Synchronous, Timing, 7-91
- - S - -
INDEX-9
I