MC68030CRC25C Freescale Semiconductor, MC68030CRC25C Datasheet - Page 362

• Manufacturer Part Number: MC68030CRC25C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030CRC25C

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

9.7.5 Register Programming Considerations
9.7.5.1 REGISTER SIDE EFFECTS.
9.7.5.2
MOTOROLA
translation registers with new values can cause some or all of the address
software. The assertion of RESET disables translations by clearing the E bits
ATC is optional under control of the FD bit of the PMOVE instruction that
The programmer of the MMU must be aware of effects resulting from loading
certain registers. A subsequent section describes these effects. The MMUSR
values lend themselves to the use of a case structure for branching to ap-
scribes the conditions that result in MMU exceptions.
any of the MMU registers (CRP, SRP, TC, MMUSR, TT0, and TT1). Since
translations to change, it may be desired to flush the ATC of its contents any
time these registers are written. The opcodes of the PMOVE instructions that
write to CRP, SRP, TC, TT0, and TT1 contain a flush disable (FD) bit that
the FD bit equals zero, the ATC is flushed during the execution of the PMOVE
status register (MMUSR) indicate conditions to which the operating system
should respond. In a typical bus error handler routine, the flows shown in
The PTEST instructions set the bits in the MMUSR appropriately, and the
9-40 shows the flow for a PTEST instruction that
If the entries in the address translation cache (ATC) are no longer valid when
a reset operation occurs, an explicit flush operation must be specified by the
of the TC and TTx registers, but it does not flush the ATC. Flushing of the
loads a new value into the SRP, CRP, -I-T0, TT1, or TC register.
propriate routines in a bus error handler. An example of a flowchart that
implements this technique is shown in another section. A third section de-
loading the root pointers, the translation control register, or the transparent
optionally flushes the ATC when these instructions are executed. If the FD
bit equals one, the ATC is not flushed when the instruction is executed. If
instruction.
Figures 9-39 and 9-40 can be used to determine the cause of an MMU fault.
program can branch to the appropriate code segment for the condition. Figure
9-39 shows the flow for a PTEST instruction for the ATC (level 0), and Figure
lation tree (levels 1-7).
M M U STATUS REGISTER
MC68030 USER'S MANUAL
DECODING.
The PMOVE instruction is used to load or read
The seven status bits in the MMU
a c c e s s e s
a n
address trans-
9-61
9