MC68030CRC25C Freescale Semiconductor, MC68030CRC25C Datasheet - Page 252

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MC68030CRC25C

Manufacturer Part Number
MC68030CRC25C
Description
IC MPU 32BIT ENHANCED 128-PGA
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MC68030CRC25C

Processor Type
M680x0 32-Bit
Speed
25MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
128-PGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
7.5.3
MOTOROLA
When HALT is asserted and BERR is not asserted, the MC68030 halts external
timing requirements provides a single-step (bus cycle to bus cycle) operation.
The HALT signal affects external bus cycles only; thus, a program that resides
the data cache) may continue executing, unaffected by the HALT signal.
a bus cycle. Negating and reasserting HALT in accordance with the correct
in the instruction cache and performs no data writes (or reads that miss in
bus activity at the next bus cycle boundary. HALT by itself does not terminate
Halt Operation
SIZ0-SIZ1 : : ~
FC0-FC2
A0-A3I
gO-O3~
STERM
RER- - ~ --/------k
"~ --E--------k
R/W . . _ j /
~ - - k _ /
CLK
SO S]
ETRY SIGNALED r
Figure 7-55, Synchronous Late Retry
$2
MC68030 USER'S MANUAL
$3
-
/
HALT
/
, = j - -
k _ _ /
k---/.
SO Sl
RETRY CYCLE
$2
$3
7-91
7

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