MC68030CRC25C Freescale Semiconductor, MC68030CRC25C Datasheet - Page 338

• Manufacturer Part Number: MC68030CRC25C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030CRC25C

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

9.5.3.3 TABLE SHARING BETWEEN TASKS.
9.5.3.4 PAGING OF TABLES.
MOTOROLA
table; thus, it can read and write the shared area. Also note that the shared
tables that describe the resident set of pages need be available in main
tables.
The page descriptor located at the address given by the indirect descriptor
set).
with different permissions. In Figure 9-23 two tasks share the memory trans-
tree for an active task be resident in main memory at once. In the same way
that only the working set of pages must reside in main memory, only the
When a task attempts to use an address that would be translated by an absent
table, the MC68030 is unable to locate a translation and takes a bus error
exception when the execution unit retries the bus cycle that caused the table
code in the descriptor corresponds to nonresident tables. This determination
can be facilitated by using the unused bits in the descriptor to store status
an invalid descriptor, it makes no interpretation (or modification) of any fields
store system-defined information in the remaining bits. Typical information
that is stored includes the reason for the invalid encoding (tables paged-out,
table (table n) is resident and all other page tables are not resident.
must not have a DT field with a long or short encoding (it must either be a
page descriptor or invalid). Otherwise, the descriptor is treated as invalid,
and the MC68030 creates an ATC entry with an error condition signaled (bit
between tasks by placing a pointer to the shared table in the address trans-
lation tables of more than one task. The upper (nonshared) tables can contain
different settings of protection bits allowing different tasks to use the area
lated by the table at the B level. Note that task
area. Task
area appears at different logical addresses for each task.
memory. This paging of tables is implemented by placing the " i n v a l i d " code
($0) in the DT field of the table descriptor that points to the absent table(s).
search to be initiated.
It is the responsibility of the system software to determine that the invalid
information concerning the invalid encoding. When the MC68030 encounters
of this descriptor other than the DT field, allowing the operating system to
region not allocated
Figure 9-24 shows an address translation table in which only a single page
" B " ,
however, has the WP bit clear in its pointer to the shared
. . . . .
MC68030 USER'S MANUAL
It is not required that the entire address translation
etc.) and possibly the disk address for nonresident
A page or pointer table can be shared
" A "
cannot write to the shaded
9-37
9