MC68030CRC25C Freescale Semiconductor, MC68030CRC25C Datasheet - Page 406

• Manufacturer Part Number: MC68030CRC25C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030CRC25C

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

10.2.2.4.2 Protocol.
MOTOROLA
The F-line operation word contains the CplD field in bits [ 9 - i l ] and 001111
The second word of the cpTRAPcc instruction format contains the coproces-
the condition CIR of the coprocessor to initiate execution of the cpTRAPcc
field in the cpTRAPcc instruction format.
the main processor initiates exception processing for the cpTRAPcc exception
in bits [8:3] t ° identify the cpTRAPcc instruction. Bits [0-2] of the cpTRAPcc
erand words.
sor condition selector in bits [0-5] and should contain zeros in bits [6-15] to
the instruction can include this information in extension words. These ex-
tension words follow the word containing the coprocessor condition selector
The operand words of the cpTRAPcc F-line operation word follow the
coprocessor-defined extension words. These operand words are not explicitly
the cpTRAPcc exception handling routines. The valid encodings for bits [0-2]
words are listed in Table 10-1. Other encodings of these bits are invalid for
the cpTRAPcc instruction.
The MC68030 transfers the condition selector to the coprocessor by writing
the word following the operation word to the condition CIR. The main pro-
F-line operation word specify the number of optional operand words in the
instruction format. The instruction format can include zero, one, or two op-
maintain compatibility with future M68000 products. This word is written to
instruction by the coprocessor.
If the coprocessor requires additional information to evaluate a condition,
used by the MC68030, but can be used to contain information referenced by
of the F-line operation word and the corresponding numbers of operand
cessor then reads the response CIR to determine its next action. The copro-
cessor can, using a response primitive, request any services necessary to
evaluate the condition. If the coprocessor returns the true condition indicator,
Figure 10-8 shows the protocol for the cpTRAPcc instructions.
Table 10-1. cpTRAPcc Opmode
MC68030 USER'S MANUAL
Opmode
010
011
100
Encodings
Instruction Format
Optional Words in
Zero
Two
One
10-19
10