TP3070V-XG National Semiconductor, TP3070V-XG Datasheet - Page 14

• Manufacturer Part Number: TP3070V-XG
• Description: IC COMBO II PCM FILTER 28PLCC
• Manufacturer: National Semiconductor
• Series: COMBO®IIr
• Type: PCM Codec/Filterr

Specifications of TP3070V-XG

• Data Interface: PCM Audio Interface
• Number Of Adcs / Dacs: 1 / 1
• Sigma Delta: No
• Voltage - Supply, Analog: ±5V
• Voltage - Supply, Digital: ±5V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-LCC (J-Lead)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *TP3070V-XG

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SERIAL CONTROL PORT TIMING
t
t
INTERFACE LATCH TIMING
t
t
t
MASTER RESET PIN
t
Symbol
DSD
DDZ
SLC
HCL
DCL
WMR
Unless otherwise noted, limits printed in BOLD characters are guaranteed for V
+70˚C (−40˚C to +85˚C for TP3070-X) by correlation with 100% electrical testing at T
correlation with other production tests and/or product design and characterization. All signals referenced to GND. Typicals
specified at V
All timing parameters are measured at V
See Definitions and Timing Conventions section for test methods information.
Timing Specifications
Note 11: Applies only to MCLK Frequencies
Timing Diagrams
Delay Time, CS Low
to CO (CI/O) Valid
Delay Time, CS or 9th CCLK
High to CO (CI/O) High
Impedance
Setup Time, IL to
CCLK 8 of Byte 1
Hold Time, IL Valid from
8th CCLK Low (Byte 1)
Delay Time CCLK 8 of
Byte 2 to IL
Duration of
Master Reset High
CC
= +5V, V
Parameter
BB
= −5V, T
1.536 MHz. At 512 kHz a 50:50
(Continued)
A
= 25˚C.
OH
FIGURE 4. Non Delayed Data Timing Mode
= 2.0V and V
Applies Only if Separate
CS used for Byte 2
−40˚C to +85˚C (TP3070-X)
Applies to Earlier of CS High or 9th
CCLK High
Interface Latch Inputs Only
Interface Latch Outputs Only
C
L
= 50 pF
OL
Conditions
= 0.7V.
14
±
2% Duty Cycle must be used.
CC
= +5V
A
= 25˚C. All other limits are assured by
Min
100
15
50
1
±
5%; V
Typ
BB
= −5V
Max
100
200
±
80
80
5%; T
A
DS008635-8
= 0˚C to
Units
ns
ns
ns
ns
ns
ns
µs