TP3070V-XG National Semiconductor, TP3070V-XG Datasheet - Page 7

• Manufacturer Part Number: TP3070V-XG
• Description: IC COMBO II PCM FILTER 28PLCC
• Manufacturer: National Semiconductor
• Series: COMBO®IIr
• Type: PCM Codec/Filterr

Specifications of TP3070V-XG

• Data Interface: PCM Audio Interface
• Number Of Adcs / Dacs: 1 / 1
• Sigma Delta: No
• Voltage - Supply, Analog: ±5V
• Voltage - Supply, Digital: ±5V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-LCC (J-Lead)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *TP3070V-XG

EN
Note 5: The MSB is always the first PCM bit shifted in or out of COMBO II.
Note 6: The “PS” bit MUST always be set to 0 for the TP3071.
Note 7: T5 is the MSB of the Time-slot assignment bit field. Time slot bits should be set to “000000” for both transmit and receive when operating in non-delayed
data timing mode.
Programmable Functions
5.0 TIME-SLOT ASSIGNMENT
COMBO II can operate in either fixed time-slot or time-slot
assignment mode for selecting the Transmit and Receive
PCM time-slots. Following power-on, the device is automati-
cally in Non-Delayed Timing mode, in which the time-slot al-
ways begins with the leading (rising) edge of frame sync in-
puts FS
with Delayed Data timing; see Figure 5 . FS
have any phase relationship with each other in BCLK period
increments.
Alternatively, the internal time-slot assignment counters and
comparators can be used to access any time-slot in a frame,
using the frame sync inputs as marker pulses for the begin-
ning of transmit and receive time-slot 0. In this mode, a
frame may consist of up to 64 time-slots of 8 bits each. A
time-slot is assigned by a 2-byte instruction as shown in
Table 1 and Table 6 . The last 6 bits of the second byte indi-
cate the selected time-slot from 0–63 using straight binary
notation. When writing a timeslot and port assignment regis-
ter, if the PCM interface is currently active, it is immediately
deactivated to prevent possible bus clashes. A new assign-
ment becomes active on the second frame following the end
of the Chip-Select for the second control byte. Rewriting of
register contents should not be performed during the talking
period of a connection to prevent waveform distortion
caused by loss of a sample which will occur with each regis-
ter write. The “EN” bit allows the PCM inputs, D
puts, D
7
0
0
1
1
V
V
V
IN
IN
IN
= +Full Scale
= 0V
= −Full Scale
X
X
0/1, as appropriate, to be enabled or disabled.
(Note 6)
and FS
PS
6
0
1
0
1
R
. Time-Slot Assignment may only be used
(Note 7)
Bit Number and Name
Assign One Binary Coded Time-Slot from 0–63
Assign One Binary Coded Time-Slot from 0–63
Assign One Binary Coded Time-Slot from 0–63
Assign One Binary Coded Time-Slot from 0–63
T
5
X
X
5
TABLE 6. Time-Slot and Port Assignment Instruction
1 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
0 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0
MSB
T
4
X
X
4
µ255 law
(Continued)
X
TABLE 5. Coding Law Conventions
and FS
R
T
LSB
X
X
3
0/1, or out-
3
R
may
T
2
X
X
2
7
T
X
X
1
1
even bit inversion
Time-Slot Assignment mode requires that the FS
pulses must conform to the delayed data timing format
shown in Figure 5 .
6.0 PORT SELECTION
On the TP3070 only, an additional capability is available; 2
Transmit serial PCM ports, D
rial PCM ports, D
two-way space switching to be implemented. Port selections
for transmit and receive are made within the appropriate
time-slot assignment instruction using the “PS” bit in the sec-
ond byte. The PS bit selects either Port 0 or Port 1. Both
ports cannot be active at the same time.
On the TP3071, only ports D
fore the “PS” bit MUST always be set to 0 for these devices.
Table 6 shows the format for the second byte of both trans-
mit and receive time-slot and port assignment instructions.
7.0 TRANSMIT GAIN INSTRUCTION BYTE 2
The transmit gain can be programmed in 0.1 dB steps by
writing to the Transmit Gain Register as defined in Table 1
and Table 7 . This corresponds to a range of 0 dBm0 levels at
VF
+6.4 dBm to −19.0 dBm in 600 ).
To calculate the binary code for byte 2 of this instruction for
any desired input 0 dBm0 level in Vrms, take the nearest in-
teger to the decimal number given by:
True A-law with
1 0 1 0 1 0 1 0
1 1 0 1 0 1 0 1
0 1 0 1 0 1 0 1
0 0 1 0 1 0 1 0
MSB
X
I between 1.619 Vrms and 0.087 Vrms (equivalent to
T
X
X
0
0
LSB
Disable D
Disable D
Disable D
Disable D
Enable D
Enable D
Enable D
Enable D
200 x log
R
0 and D
X
R
X
R
X
R
X
R
0 Output (Transmit Instruction)
0 Input (Receive Instruction)
1 Output (Transmit Instruction)
1 Input (Receive Instruction)
0 Output (Transmit Instruction)
1 Output (Transmit Instruction)
0 Input (Receive Instruction)
1 Input (Receive Instruction)
10
X
X
0 and D
0 and D
(V/0.08595)
R
even bit inversion
1, are provided to enable
Function
1 1 1 1 1 1 1 1
1 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 1 1 1 1 1 1 1
A-law without
MSB
R
X
0 are available, there-
1, and 2 Receive se-
LSB
www.national.com
X
and FS
R