PIC32MX664F064LT-I/PT Microchip Technology Inc., PIC32MX664F064LT-I/PT Datasheet - Page 125

• Manufacturer Part Number: PIC32MX664F064LT-I/PT
• Description: 100 TQFP 12X12X1MM T/R, 100 PINS, 64KB FLASH, 32KB RAM, 80 MHZ, USB, ETHERNET, 4
• Manufacturer: Microchip Technology Inc.

Specifications of PIC32MX664F064LT-I/PT

• A/d Inputs: 16-Channel, 10-Bit
• Comparators: 2
• Eeprom Memory: 0 Bytes
• Input Output: 85
• Interface: I2C/SPI/UART/USB
• Memory Type: Flash
• Number Of Bits: 32
• Package Type: 100-pin TQFP
• Programmable Memory: 64K Bytes
• Ram Size: 32K Bytes
• Speed: 80 MHz
• Temperature Range: –40 to +85 °C
• Timers: 5-16-bit
• Voltage, Range: 2.3-3.6 V
• Lead Free Status / Rohs Status: RoHS Compliant part

10.0
The PIC32 Direct Memory Access (DMA) controller is a
bus master module useful for data transfers between
different devices without CPU intervention. The source
and destination of a DMA transfer can be any of the
memory mapped modules existent in the PIC32 (such
as Peripheral Bus (PBUS) devices: SPI, UART, PMP,
etc.) or memory itself.
Following are some of the key features of the DMA
controller module:
• Four identical channels, each featuring:
FIGURE 10-1:
© 2010 Microchip Technology Inc.
- Auto-increment source and destination
- Source and destination pointers
- Memory to memory and memory to
INT Controller
Note 1: This data sheet summarizes the features
address registers
peripheral transfers
Peripheral Bus
2: Some registers and associated bits
DIRECT MEMORY ACCESS
(DMA) CONTROLLER
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 31. “Direct
Memory Access (DMA) Controller”
(DS61117)
Reference Manual” , which is available
from
(www.microchip.com/PIC32).
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization”
this data sheet for device-specific register
and bit information.
the
Address Decoder
Global Control
DMA BLOCK DIAGRAM
(DMACON)
in
Microchip
the
System IRQ
“PIC32
web
Family
Channel n Control
Channel 0 Control
Channel 1 Control
site
in
• Automatic word-size detection:
• Fixed priority channel arbitration
• Flexible DMA channel operating modes:
• Flexible DMA requests:
• Multiple DMA channel status interrupts:
• DMA debug support features:
• CRC Generation module:
Channel Priority
PIC32MX5XX/6XX/7XX
- Transfer granularity, down to byte level
- Bytes need not be word-aligned at source
- Manual (software) or automatic (interrupt)
- One-Shot or Auto-Repeat Block Transfer
- Channel-to-channel chaining
- A DMA request can be selected from any of
- Each channel can select any (appropriate)
- A DMA transfer abort can be selected from
- Pattern (data) match transfer termination
- DMA channel block transfer complete
- Source empty or half empty
- Destination full or half full
- DMA transfer aborted due to an external
- Invalid DMA address generated
- Most recent address accessed by a DMA
- Most recent DMA channel to transfer data
- CRC module can be assigned to any of the
- CRC module is highly configurable
Arbitration
I
I
I
I
and destination
DMA requests
modes
the peripheral interrupt sources
observable interrupt as its DMA request
source
any of the peripheral interrupt sources
event
channel
available channels
0
1
2
n
Y
Bus Interface
Device Bus + Bus Arbitration
DS61156F-page 125