K4S643232H-TI70 Samsung Semiconductor, K4S643232H-TI70 Datasheet - Page 10

• Manufacturer Part Number: K4S643232H-TI70
• Manufacturer: Samsung Semiconductor

Specifications of K4S643232H-TI70

• Lead Free Status / Rohs Status: Not Compliant

AC OPERATING TEST CONDITIONS
K4S643232H
(AC operating conditions unless otherwise noted)
AC input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
OPERATING AC PARAMETER
Note :
Row active to row active delay
RAS to CAS delay
Row precharge time
Row active time
Row cycle time
Last data in to row precharge
Last data in to new col.address delay
Last data in to burst stop
Col. address to col. address delay
Mode Register Set cycle time
Number of valid
output data
Output
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
rounding off to the next higher integer. Refer to the following ns-unit based AC table.
(Fig. 1) DC output load circuit
Parameter
870Ω
Parameter
CAS Latency=3
CAS Latency=2
3.3V
1200Ω
50pF
t
t
Symbol
t
t
t
t
t
t
t
RAS(max)
t
MRS(min)
RRD(min)
RCD(min)
t
RAS(min)
CCD(min)
RDL(min)
CDL(min)
BDL(min)
RC
RP(min)
(
min
V
V
OH
OL
)
(DC) = 0.4V, I
(V
(DC) = 2.4V, I
DD
= 3.3V ± 0.3V, T
50
11
3
3
8
OL
OH
- 10
= 2mA
= -2mA
A
= 0 to 70°C)
55
10
3
3
7
See Fig. 2
tr/tf = 1/1
2.4/0.4
Value
1.4
1.4
Version
Output
100
2
2
1
1
1
2
2
1
60
10
3
3
7
(Fig. 2) AC output load circuit
Z0 = 50Ω
Rev. 1.2 April 2006
70
10
3
3
7
Unit
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
SDRAM
Vtt = 1.4V
Unit
us
ea
50Ω
ns
50pF
V
V
V
Note
1
1
1
1
1
2
2
2
3
4