K4S643232H-TI70 Samsung Semiconductor, K4S643232H-TI70 Datasheet - Page 3

• Manufacturer Part Number: K4S643232H-TI70
• Manufacturer: Samsung Semiconductor

Specifications of K4S643232H-TI70

• Lead Free Status / Rohs Status: Not Compliant

K4S643232H
with SAMSUNG′s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock.
I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable
latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
512K x 32Bit x 4 Banks
FEATURES
• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
• All inputs are sampled at the positive going edge of the system clock.
• Burst read single-bit write operation
• DQM (x4,x8) & L(U)DQM (x16) for masking
• Auto & self refresh
• 15.6us refresh duty cycle
•
•
GENERAL DESCRIPTION
Ordering Information
The K4S643232H is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 524,288 words by 32 bits, fabricated
Pb-free Package
RoHS compliant
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
K4S643232H-UC/L70
K4S643232H-UC/L60
K4S643232H-UC/L55
K4S643232H-UC/L50
Part No.
Organization
2Mx32
Row & Column address configuration
Orgainization
2Mbx32
Row Address
A0~A10
- 3 -
Max Freq.
143MHz
166MHz
183MHz
200MHz
Column Address
A0-A7
Interface
LVTTL
LVTTL
LVTTL
LVTTL
Rev. 1.2 April 2006
86pin TSOP(II)
86pin TSOP(II)
86pin TSOP(II)
86pin TSOP(II)
Package
SDRAM