K4S643232H-TI70 Samsung Semiconductor, K4S643232H-TI70 Datasheet - Page 16

• Manufacturer Part Number: K4S643232H-TI70
• Manufacturer: Samsung Semiconductor

Specifications of K4S643232H-TI70

• Lead Free Status / Rohs Status: Not Compliant

Device Operation &
Timing Diagram
DEVICE OPERATIONS (Continued)
MODE REGISTER SET (MRS)
The mode register stores the data for controlling the various
operating modes of SDRAM. It programs the CAS latency, burst
type, burst length, test mode and various vendor specific options
to make SDRAM useful for variety of different applications. The
default value of the mode register is not defined, therefore the
mode register must be written after power up to operate the
SDRAM. The mode register is written by asserting low on CS,
RAS, CAS and WE (The SDRAM should be in active mode with
CKE already high prior to writing the mode register). The state of
address pins A
RAS, CAS and WE going low is the data written in the mode
register. Two clock cycles is required to complete the write in the
mode register. The mode register contents can be changed
using the same command and clock cycle requirements during
operation as long as all banks are in the idle state. The mode
register is divided into various fields depending on the fields of
functions. The burst length field uses A
A
A
and BA
A
SDRAM operation. Refer to the table for specific codes for vari-
ous burst length, burst type and CAS latencies.
BANK ACTIVATE
The bank activate command is used to select a random row in
an idle bank. By asserting low on RAS and CS with desired row
and bank address, a row access is initiated. The read or write
operation can occur after a time delay of t
of bank activation. t
SDRAM, therefore it is dependent on operating clock frequency.
The minimum number of clock cycles required between bank
activate and read or write command should be calculated by
dividing t
off the result to the next higher integer. The SDRAM has four
internal banks in the same chip and shares part of the internal
circuitry to reduce chip area, therefore it restricts the activation
of four banks simultaneously. Also the noise generated during
sensing of each bank of SDRAM is high, requiring some time for
power supplies to recover before another bank can be sensed
reliably. t
activating different bank. The number of clock cycles required
between different bank activation must be calculated similar to
t
RCD
3
6
7
, CAS latency (read latency from column address) use A
, vendor specific options or test mode use A
~ A
specification. The minimum time required for the bank to be
8
0
, A
RCD
RRD
~ BA
10
/AP and BA
(min) with cycle time of the clock and then rounding
(min) specifies the minimum time required between
1
0
. The write burst length is programmed using A
~ A
10
RCD
and BA
0
~ BA
is an internal timing parameter of
0
~ BA
1
must be set to low for normal
1
in the same cycle as CS,
0
RCD
~ A
(min) from the time
2
, burst type uses
7
~ A
8
, A
10
/AP
4
9
~
.
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active to initiate sensing and restoring the complete row of
dynamic cells is determined by t
activate command must satisfy t
precharge command to that active bank can be asserted. The
maximum time any bank can be in the active state is determined
by t
t
BURST READ
The burst read command is used to access burst of data on con-
secutive clock cycles from an active row in an active bank. The
burst read command is issued by asserting low on CS and CAS
with WE being high on the positive edge of the clock. The bank
must be active for at least t
mand is issued. The first output appears in CAS latency number
of clock cycles after the issue of burst read command. The burst
length, burst sequence and latency from the burst read com-
mand is determined by the mode register which is already pro-
grammed. The burst read can be initiated on any column
address of the active row. The address wraps around if the initial
address does not start from a boundary such that number of out-
puts from each I/O are equal to the burst length programmed in
the mode register. The output goes into high-impedance at the
end of the burst, unless a new burst read was initiated to keep
the data output gapless. The burst read can be terminated by
issuing another burst read or burst write in the same bank or the
other active bank or a precharge command to the same bank.
The burst stop command is valid at every page burst length.
BURST WRITE
The burst write command is similar to burst read command and
is used to write data into the SDRAM on consecutive clock
cycles in adjacent addresses depending on burst length and
burst sequence. By asserting low on CS, CAS and WE with valid
column address, a write burst is initiated. The data inputs are
provided for the initial address in the same clock cycle as the
burst write command. The input buffer is deselected at the end
of the burst length, even though the internal writing can be com-
pleted yet. The writing can be completed by issuing a burst read
and DQM for blocking data inputs or burst write in the same or
another active bank. The burst stop command is valid at every
burst length. The write burst can also be terminated by using
DQM for blocking data and procreating the bank t
last data input to be written into the active row. See DQM
OPERATION also.
RAS
RAS
(max) can be calculated similar to t
(max). The number of cycles for both t
RCD
(min) before the burst read com-
RAS
Rev. 1.2 April 2006
RAS
(min) specification before a
(min). Every SDRAM bank
RCD
x32 SDRAM
specification.
RAS
RDL
(min) and
after the