K4S643232H-TI70 Samsung Semiconductor, K4S643232H-TI70 Datasheet - Page 15

• Manufacturer Part Number: K4S643232H-TI70
• Manufacturer: Samsung Semiconductor

Specifications of K4S643232H-TI70

• Lead Free Status / Rohs Status: Not Compliant

Device Operation &
Timing Diagram
DEVICE OPERATIONS
CLOCK (CLK)
The clock input is used as the reference for all SDRAM opera-
tions. All operations are synchronized to the positive going edge
of the clock. The clock transitions must be monotonic between
V
assumed to be in a valid state (low or high) for the duration of
set-up and hold time around positive edge of the clock in order
to function well Q perform and I
CLOCK ENABLE (CKE)
The clock enable(CKE) gates the clock onto SDRAM. If CKE
goes low synchronously with clock (set-up and hold time are the-
same as other inputs), the internal clock is suspended from the
next clock cycle and the state of output and burst address is fro-
zen as long as the CKE remains low. All other inputs are ignored
from the next clock cycle after CKE goes low. When all banks
are in the idle state and CKE goes low synchronously with clock,
the SDRAM enters the power down mode from the next clock
cycle. The SDRAM remains in the power down mode ignoring
the other inputs as long as CKE remains low. The power down
exit is synchronous as the internal clock is suspended. When
CKE goes high at least "1CLK + t
of the clock, then the SDRAM becomes active from the same
clock edge accepting all the input commands.
BANK ADDRESSES (BA0 ~ BA1)
This SDRAM is organized as four independent banks of 524,288
words x 32 bits memory arrays. The BA
latched at the time of assertion of RAS and CAS to select the
bank to be used for the operation. The bank addresses BA
BA
and precharge operations.
ADDRESS INPUTS (A0 ~ A10)
The 19 address bits are required to decode the 524,288 word
locations are multiplexed into 11 address input pins (A
The 11 bit row addresses are latched along with RAS and BA
BA
are latched along with CAS, WE and BA
write command.
IL
1
1
and V
during bank activate command. The 8 bit column addresses
are latched at bank active, read, write, mode register set
IH
. During operation with CKE high all inputs are
CC
SS
specifications.
" before the high going edge
0
~ BA
0
~ BA
1
during read or
1
inputs are
0
~ A
10
0
0
).
~
~
- 15
NOP and DEVICE DESELECT
When RAS, CAS and WE are high, the SDRAM performs no
operation (NOP). NOP does not initiate any new operation, but
is needed to complete operations which require more than sin-
gle clock cycle like bank activate, burst read, auto refresh, etc.
The device deselect is also a NOP and is entered by asserting
CS high. CS high disables the command decoder so that RAS,
CAS, WE and all the address inputs are ignored.
POWER-UP
defined manner to prevent undefined operations.
1. Apply power and start clock. Must maintain CKE= "H", DQM=
2. Maintain stable power, stable clock and NOP input condition
3. Issue precharge commands for both banks of the devices.
4. Issue 2 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode reg-
cf.) Sequence of 4 & 5 is regardless of the order.
SDRAMs must be powered up and initialized in a pre-
"H" and the other pins are NOP condition at the inputs.
for a minimum of 200us.
ister.
The device is now ready for normal operation.
Rev. 1.2 April 2006
x32 SDRAM