K4S643232H-TI70 Samsung Semiconductor, K4S643232H-TI70 Datasheet - Page 23

• Manufacturer Part Number: K4S643232H-TI70
• Manufacturer: Samsung Semiconductor

Specifications of K4S643232H-TI70

• Lead Free Status / Rohs Status: Not Compliant

Device Operation &
Timing Diagram
10. Clock Suspend Exit & Power Down Exit
11. Auto Refresh & Self Refresh
*Note : 1. Active power down : one or more banks active state.
2) Self Refresh
1) Clock Suspend (=Active Power Down) Exit
1) Auto Refresh
2. Precharge power down : all banks precharge state.
3. The auto refresh is the same as CBR refresh of conventional DRAM.
4. Before executing auto/self refresh command, all banks must be idle state.
5. MRS, Bank Active, Auto/Self Refresh, Power Down Mode Entry.
6. During self refresh mode, refresh interval and refresh operation are perfomed internally.
Internal
No precharge commands are required after auto refresh command.
During t
After self refresh entry, self refresh mode is kept while CKE is low.
During self refresh mode, all inputs expect CKE will be don't cared, and outputs will be in Hi-Z state.
For the time interval of t
Before/After self refresh mode, burst auto refresh cycle (4096 cycles) is recommended.
CMD
CMD
CMD
CKE
CLK
CLK
CLK
CKE
CLK
CKE
RFC
from auto refresh command, any other command can not be accepted.
Note 6
Note 1
Note 3
PRE
PRE
RFC
Note 4
Note 4
from self refresh exit command, any other command can not be accepted.
tRP
tRP
tSS
AR
SR
RD
¡ó
¡ó
tRFC
¡ó
¡ó
¡ó
¡ó
- 23
2) Power Down (=Precharge Power Down) Exit
Internal
¡ó
CMD
CMD
CKE
CLK
CLK
tRFC
Note 5
Note 2
CMD
Rev. 1.2 April 2006
NOP
tSS
ACT
x32 SDRAM