TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 227

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

9.6.4
synchronously. In the TMPM330FDFG/FYFG/FWFG, the following combinations allow to use.
Setting of start timing for TBxRUN<TBPRUN, TBRUN> bit in the slave channel is not required.
Timer synchronous mode
This mode enables the timers to start synchronously.
If the mode is used with PPG output, the output can be applied to drive a motor.
TMRB is consisted of two pairs of 4-channel TMRB. If one channel starts, remaining 3 channels can be start
Use of the timer synchronous mode is specified in TBxCR<TBSYNC> bit.
Set "0" to the <TBSYNC> bit in the master channel.
If <TBSYNC>= "1" is set in the slave channel, the start timing is synchronized with master channel start timing.
・ <TBSYNC> = "0" : Timer operates individually.
・ <TBSYNC> = "1" : Timers operates synchronously.
Start trigger channel
(Master channel)
TMRB0
TMRB4
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Synchronous operation channel
TMRB1, TMRB2, TMRB3
TMRB5, TMRB6, TMRB7
(Slave channel)
TMPM330FDFG/FYFG/FWFG