TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 89

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

7.5.2
standby mode
Not clearing
7.5.2.1
Settings for sending interrupt
(clearing standby mode)
CG detects interrupt
CPU handles interrupt
CPU detects interrupt
Settings for detection
Interrupt generation
Interrupt Handling
Processing
signal
The following shows how an interrupt is handled.
Flowchart
In the following descriptions,
handling.
standby mode
Clearing
Set the relevant NVIC registers for detecting interrupts.
Set the clock generator as well if each interrupt source is used to clear a standby
mode.
οCommon setting
NVIC registers
οSetting to clear standby mode
Clock generator
Execute an appropriate setting to send the interrupt signal depending on the in-
terrupt type.
οSetting for interrupt from external pin
Port
οSetting for interrupt from peripheral function
Peripheral function (See the chapter of each peripheral function for details.)
An interrupt request is generated.
Interrupt lines used for clearing a standby mode are connected to the CPU via
the clock generator.
The CPU detects the interrupt.
If multiple interrupt requests occur simultaneously, the interrupt request with the
highest priority is detected according to the priority order.
The CPU handles the interrupt.
The CPU pushes register contents to the stack before entering the ISR.
Page 69
indicates hardware handling.
Details
TMPM330FDFG/FYFG/FWFG
indicates software
"7.5.2.2 Preparation"
"7.5.2.3 Detection by
"7.5.2.4 Detection by
Clock Generator"
"7.5.2.5 CPU pro-
cessing"
CPU"
See